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0cc6f45cec
Including: - Core: - IOMMU memory usage observability - This will make the memory used for IO page tables explicitly visible. - Simplify arch_setup_dma_ops() - Intel VT-d: - Consolidate domain cache invalidation - Remove private data from page fault message - Allocate DMAR fault interrupts locally - Cleanup and refactoring - ARM-SMMUv2: - Support for fault debugging hardware on Qualcomm implementations - Re-land support for the ->domain_alloc_paging() callback - ARM-SMMUv3: - Improve handling of MSI allocation failure - Drop support for the "disable_bypass" cmdline option - Major rework of the CD creation code, following on directly from the STE rework merged last time around. - Add unit tests for the new STE/CD manipulation logic - AMD-Vi: - Final part of SVA changes with generic IO page fault handling - Renesas IPMMU: - Add support for R8A779H0 hardware - A couple smaller fixes and updates across the sub-tree -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmZHJMkACgkQK/BELZcB GuND1Q/+M4RN5jM66XCfhqoP8QaI8I7zDlPDd14ismx0bjtOZhoiXpptKkAA8guo 7mS57MLqBw/hKYucm1mw+F1qi1HnRWSstKXiCPmzDm3UXYgZJlKkrOw6vydFeHJH zx2ei7TmBrc0SrsybWK3NWRfVBBkO8enGZTmti0DfHL/rOFcUM0LHegY51GcDaaH SlDr+LLDMeGynSQWhRlVNJVmEI5gpVPitY/mDUpVPoELiW9C0WGk8kPlR11z2pCR eUNiqGJUcGasOhmfiYnpJR462eg7J41glquu+YHj8ivPbbu3C4wxgruY/tR4dmJG 8s6AMAWR53JzG2SrCCwtzyRPSXmKfvixF+VKmlB2Ksc7VAn1xA0DYnY5Tx99EtXu qcEaR4SICMti0urmBGo/cGFdXi2TB1ccXqwoRtp1N3KiYnnOaQdLNO9qZdl9uUTI uleXACzkCVSssSpBfGjFcPyHU4r3WjMfX0f5ZJPpFMoQmvwV1yeMX7xTEZz4Sxew cHfBt9FAW9+4mBMTQfokBt0hZ6jwKcYl/z3Xi2oD+Ik/Qrzx5kcLA8LZLEVRXIBa SZh2ASazq/dr8YoZ744VRmlmi+nISAIHbbQMeqQEQgYQh0HpwS9g5HtpsBzNP6aB 91RHqZSccb/zNdi8e+RH79Y7pX/G5QcuVKcW6KQUBcAAb6hAgOg= =JUzp -----END PGP SIGNATURE----- Merge tag 'iommu-updates-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: "Core: - IOMMU memory usage observability - This will make the memory used for IO page tables explicitly visible. - Simplify arch_setup_dma_ops() Intel VT-d: - Consolidate domain cache invalidation - Remove private data from page fault message - Allocate DMAR fault interrupts locally - Cleanup and refactoring ARM-SMMUv2: - Support for fault debugging hardware on Qualcomm implementations - Re-land support for the ->domain_alloc_paging() callback ARM-SMMUv3: - Improve handling of MSI allocation failure - Drop support for the "disable_bypass" cmdline option - Major rework of the CD creation code, following on directly from the STE rework merged last time around. - Add unit tests for the new STE/CD manipulation logic AMD-Vi: - Final part of SVA changes with generic IO page fault handling Renesas IPMMU: - Add support for R8A779H0 hardware ... and a couple smaller fixes and updates across the sub-tree" * tag 'iommu-updates-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (80 commits) iommu/arm-smmu-v3: Make the kunit into a module arm64: Properly clean up iommu-dma remnants iommu/amd: Enable Guest Translation after reading IOMMU feature register iommu/vt-d: Decouple igfx_off from graphic identity mapping iommu/amd: Fix compilation error iommu/arm-smmu-v3: Add unit tests for arm_smmu_write_entry iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd() iommu/arm-smmu-v3: Move the CD generation for SVA into a function iommu/arm-smmu-v3: Allocate the CD table entry in advance iommu/arm-smmu-v3: Make arm_smmu_alloc_cd_ptr() iommu/arm-smmu-v3: Consolidate clearing a CD table entry iommu/arm-smmu-v3: Move the CD generation for S1 domains into a function iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry() iommu/arm-smmu-v3: Add an ops indirection to the STE code iommu/arm-smmu-qcom: Don't build debug features as a kernel module iommu/amd: Add SVA domain support iommu: Add ops->domain_alloc_sva() iommu/amd: Initial SVA support for AMD IOMMU iommu/amd: Add support for enable/disable IOPF iommu/amd: Add IO page fault notifier handler ...
168 lines
3.6 KiB
C
168 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/cpumask.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/msi.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/irqdomain.h>
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#include <asm/hw_irq.h>
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#include <asm/irq_remapping.h>
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#include <asm/processor.h>
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#include <asm/x86_init.h>
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#include <asm/apic.h>
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#include <asm/hpet.h>
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#include "irq_remapping.h"
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int irq_remapping_enabled;
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int irq_remap_broken;
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int disable_sourceid_checking;
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int no_x2apic_optout;
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int disable_irq_post = 0;
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bool enable_posted_msi __ro_after_init;
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static int disable_irq_remap;
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static struct irq_remap_ops *remap_ops;
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static void irq_remapping_restore_boot_irq_mode(void)
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{
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/*
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* With interrupt-remapping, for now we will use virtual wire A
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* mode, as virtual wire B is little complex (need to configure
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* both IOAPIC RTE as well as interrupt-remapping table entry).
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* As this gets called during crash dump, keep this simple for
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* now.
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*/
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if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
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disconnect_bsp_APIC(0);
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}
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static void __init irq_remapping_modify_x86_ops(void)
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{
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x86_apic_ops.restore = irq_remapping_restore_boot_irq_mode;
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}
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static __init int setup_nointremap(char *str)
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{
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disable_irq_remap = 1;
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return 0;
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}
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early_param("nointremap", setup_nointremap);
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static __init int setup_irqremap(char *str)
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{
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if (!str)
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return -EINVAL;
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while (*str) {
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if (!strncmp(str, "on", 2)) {
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disable_irq_remap = 0;
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disable_irq_post = 0;
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} else if (!strncmp(str, "off", 3)) {
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disable_irq_remap = 1;
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disable_irq_post = 1;
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} else if (!strncmp(str, "nosid", 5))
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disable_sourceid_checking = 1;
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else if (!strncmp(str, "no_x2apic_optout", 16))
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no_x2apic_optout = 1;
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else if (!strncmp(str, "nopost", 6))
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disable_irq_post = 1;
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else if (IS_ENABLED(CONFIG_X86_POSTED_MSI) && !strncmp(str, "posted_msi", 10))
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enable_posted_msi = true;
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str += strcspn(str, ",");
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while (*str == ',')
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str++;
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}
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return 0;
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}
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early_param("intremap", setup_irqremap);
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void set_irq_remapping_broken(void)
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{
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irq_remap_broken = 1;
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}
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bool irq_remapping_cap(enum irq_remap_cap cap)
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{
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if (!remap_ops || disable_irq_post)
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return false;
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return (remap_ops->capability & (1 << cap));
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}
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EXPORT_SYMBOL_GPL(irq_remapping_cap);
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int __init irq_remapping_prepare(void)
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{
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if (disable_irq_remap)
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return -ENOSYS;
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if (IS_ENABLED(CONFIG_INTEL_IOMMU) &&
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intel_irq_remap_ops.prepare() == 0)
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remap_ops = &intel_irq_remap_ops;
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else if (IS_ENABLED(CONFIG_AMD_IOMMU) &&
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amd_iommu_irq_ops.prepare() == 0)
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remap_ops = &amd_iommu_irq_ops;
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else if (IS_ENABLED(CONFIG_HYPERV_IOMMU) &&
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hyperv_irq_remap_ops.prepare() == 0)
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remap_ops = &hyperv_irq_remap_ops;
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else
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return -ENOSYS;
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return 0;
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}
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int __init irq_remapping_enable(void)
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{
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int ret;
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if (!remap_ops->enable)
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return -ENODEV;
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ret = remap_ops->enable();
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if (irq_remapping_enabled)
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irq_remapping_modify_x86_ops();
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return ret;
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}
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void irq_remapping_disable(void)
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{
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if (irq_remapping_enabled && remap_ops->disable)
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remap_ops->disable();
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}
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int irq_remapping_reenable(int mode)
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{
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if (irq_remapping_enabled && remap_ops->reenable)
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return remap_ops->reenable(mode);
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return 0;
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}
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int __init irq_remap_enable_fault_handling(void)
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{
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if (!irq_remapping_enabled)
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return 0;
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if (!remap_ops->enable_faulting)
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return -ENODEV;
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cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "dmar:enable_fault_handling",
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remap_ops->enable_faulting, NULL);
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return remap_ops->enable_faulting(smp_processor_id());
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}
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void panic_if_irq_remap(const char *msg)
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{
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if (irq_remapping_enabled)
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panic(msg);
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}
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