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c430131a02
The two first HC capability registers (CAPLENGTH and HCIVERSION) are defined as one 8-bit and one 16-bit register. Most HC implementations have selected to treat these registers as part of a 32-bit register, giving the same layout for both big and small endian systems. This patch adds a new quirk, big_endian_capbase, to support controllers with big endian register interfaces that treat HCIVERSION and CAPLENGTH as individual registers. Signed-off-by: Jan Andersson <jan@gaisler.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
172 lines
4.2 KiB
C
172 lines
4.2 KiB
C
/*
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* Copyright 2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/atomic.h>
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#include <mach/cns3xxx.h>
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#include <mach/pm.h>
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static int cns3xxx_ehci_init(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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int retval;
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*
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* Set USB AHB INCR length to 16
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*/
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if (atomic_inc_return(&usb_pwr_ref) == 1) {
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cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
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cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
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__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
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MISC_CHIP_CONFIG_REG);
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}
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs
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+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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hcd->has_tt = 0;
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ehci_reset(ehci);
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retval = ehci_init(hcd);
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if (retval)
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return retval;
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ehci_port_power(ehci, 0);
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return retval;
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}
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static const struct hc_driver cns3xxx_ehci_hc_driver = {
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.description = hcd_name,
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.product_desc = "CNS3XXX EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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.irq = ehci_irq,
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.flags = HCD_MEMORY | HCD_USB2,
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.reset = cns3xxx_ehci_init,
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.start = ehci_run,
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.stop = ehci_stop,
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.shutdown = ehci_shutdown,
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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.endpoint_reset = ehci_endpoint_reset,
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.get_frame_number = ehci_get_frame,
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.hub_status_data = ehci_hub_status_data,
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.hub_control = ehci_hub_control,
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#ifdef CONFIG_PM
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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#endif
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.relinquish_port = ehci_relinquish_port,
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.port_handed_over = ehci_port_handed_over,
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.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
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};
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static int cns3xxx_ehci_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct usb_hcd *hcd;
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const struct hc_driver *driver = &cns3xxx_ehci_hc_driver;
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struct resource *res;
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int irq;
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int retval;
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if (usb_disabled())
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return -ENODEV;
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!res) {
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dev_err(dev, "Found HC with no IRQ.\n");
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return -ENODEV;
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}
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irq = res->start;
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hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
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if (!hcd)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "Found HC with no register addr.\n");
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retval = -ENODEV;
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goto err1;
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}
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hcd->rsrc_start = res->start;
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hcd->rsrc_len = res->end - res->start + 1;
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if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
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driver->description)) {
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dev_dbg(dev, "controller already in use\n");
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retval = -EBUSY;
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goto err1;
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}
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hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
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if (hcd->regs == NULL) {
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dev_dbg(dev, "error mapping memory\n");
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retval = -EFAULT;
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goto err2;
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}
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retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
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if (retval == 0)
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return retval;
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iounmap(hcd->regs);
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err2:
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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err1:
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usb_put_hcd(hcd);
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return retval;
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}
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static int cns3xxx_ehci_remove(struct platform_device *pdev)
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{
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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usb_remove_hcd(hcd);
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iounmap(hcd->regs);
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*/
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if (atomic_dec_return(&usb_pwr_ref) == 0)
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cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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usb_put_hcd(hcd);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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MODULE_ALIAS("platform:cns3xxx-ehci");
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static struct platform_driver cns3xxx_ehci_driver = {
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.probe = cns3xxx_ehci_probe,
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.remove = cns3xxx_ehci_remove,
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.driver = {
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.name = "cns3xxx-ehci",
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},
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};
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