Stefan Eichenberger 8c9f085ae3 phy: marvell: phy-mvebu-cp110-comphy: improve eth_port1 on comphy4 ... According to the CN9100_MPP_information document, CP_SRD4 (comphy 4) supports 2500 BASE-X and 5000 BASE-R for ETH_PORT1. I was able to test that 2500 BASE-X is indeed supported. Unfortunately, our HW does not support 5000 BASE-R, but I assume from the document that it does, so I set the muxing there too to 0x1. Signed-off-by: Stefan Eichenberger <eichest@gmail.com> Link: https://lore.kernel.org/r/20240711131612.98952-1-eichest@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2024-08-04 22:52:11 +05:30
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Kconfig
Makefile
phy-armada38x-comphy.c	phy: constify of_phandle_args in xlate	2024-02-23 17:43:14 +05:30
phy-armada375-usb2.c	phy: constify of_phandle_args in xlate	2024-02-23 17:43:14 +05:30
phy-berlin-sata.c	phy: constify of_phandle_args in xlate	2024-02-23 17:43:14 +05:30
phy-berlin-usb.c	phy: Use device_get_match_data()	2023-10-13 15:45:40 +05:30
phy-mmp3-hsic.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
phy-mmp3-usb.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
phy-mvebu-a3700-comphy.c	phy: marvell: a3700-comphy: Fix hardcoded array size	2024-04-05 22:32:00 +05:30
phy-mvebu-a3700-utmi.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
phy-mvebu-cp110-comphy.c	phy: marvell: phy-mvebu-cp110-comphy: improve eth_port1 on comphy4	2024-08-04 22:52:11 +05:30
phy-mvebu-cp110-utmi.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
phy-mvebu-sata.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
phy-pxa-28nm-hsic.c	phy: marvell: drop of_match_ptr for ID table	2023-03-20 18:14:59 +05:30
phy-pxa-28nm-usb2.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
phy-pxa-usb.c	phy: marvell pxa-usb: fix Wvoid-pointer-to-enum-cast warning	2023-08-11 09:25:15 +01:00