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Add docs on extended 64-bit immediate instructions, including six instructions previously undocumented. Include a brief description of maps and variables, as used by those instructions. V1 -> V2: rebased on top of latest master V2 -> V3: addressed comments from Alexei V3 -> V4: addressed comments from David Vernet Signed-off-by: Dave Thaler <dthaler@microsoft.com> Link: https://lore.kernel.org/r/20230326054946.2331-1-dthaler1968@googlemail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
476 lines
19 KiB
ReStructuredText
476 lines
19 KiB
ReStructuredText
.. contents::
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.. sectnum::
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========================================
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eBPF Instruction Set Specification, v1.0
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========================================
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This document specifies version 1.0 of the eBPF instruction set.
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Documentation conventions
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=========================
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For brevity, this document uses the type notion "u64", "u32", etc.
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to mean an unsigned integer whose width is the specified number of bits,
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and "s32", etc. to mean a signed integer of the specified number of bits.
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Registers and calling convention
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================================
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eBPF has 10 general purpose registers and a read-only frame pointer register,
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all of which are 64-bits wide.
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The eBPF calling convention is defined as:
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* R0: return value from function calls, and exit value for eBPF programs
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* R1 - R5: arguments for function calls
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* R6 - R9: callee saved registers that function calls will preserve
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* R10: read-only frame pointer to access stack
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R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if
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necessary across calls.
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Instruction encoding
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====================
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eBPF has two instruction encodings:
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* the basic instruction encoding, which uses 64 bits to encode an instruction
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* the wide instruction encoding, which appends a second 64-bit immediate (i.e.,
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constant) value after the basic instruction for a total of 128 bits.
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The fields conforming an encoded basic instruction are stored in the
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following order::
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opcode:8 src_reg:4 dst_reg:4 offset:16 imm:32 // In little-endian BPF.
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opcode:8 dst_reg:4 src_reg:4 offset:16 imm:32 // In big-endian BPF.
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**imm**
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signed integer immediate value
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**offset**
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signed integer offset used with pointer arithmetic
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**src_reg**
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the source register number (0-10), except where otherwise specified
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(`64-bit immediate instructions`_ reuse this field for other purposes)
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**dst_reg**
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destination register number (0-10)
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**opcode**
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operation to perform
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Note that the contents of multi-byte fields ('imm' and 'offset') are
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stored using big-endian byte ordering in big-endian BPF and
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little-endian byte ordering in little-endian BPF.
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For example::
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opcode offset imm assembly
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src_reg dst_reg
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07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little
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dst_reg src_reg
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07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big
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Note that most instructions do not use all of the fields.
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Unused fields shall be cleared to zero.
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As discussed below in `64-bit immediate instructions`_, a 64-bit immediate
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instruction uses a 64-bit immediate value that is constructed as follows.
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The 64 bits following the basic instruction contain a pseudo instruction
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using the same format but with opcode, dst_reg, src_reg, and offset all set to zero,
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and imm containing the high 32 bits of the immediate value.
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This is depicted in the following figure::
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basic_instruction
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.-----------------------------.
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code:8 regs:8 offset:16 imm:32 unused:32 imm:32
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'--------------'
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pseudo instruction
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Thus the 64-bit immediate value is constructed as follows:
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imm64 = (next_imm << 32) | imm
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where 'next_imm' refers to the imm value of the pseudo instruction
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following the basic instruction. The unused bytes in the pseudo
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instruction are reserved and shall be cleared to zero.
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Instruction classes
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-------------------
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The three LSB bits of the 'opcode' field store the instruction class:
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========= ===== =============================== ===================================
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class value description reference
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========= ===== =============================== ===================================
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BPF_LD 0x00 non-standard load operations `Load and store instructions`_
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BPF_LDX 0x01 load into register operations `Load and store instructions`_
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BPF_ST 0x02 store from immediate operations `Load and store instructions`_
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BPF_STX 0x03 store from register operations `Load and store instructions`_
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BPF_ALU 0x04 32-bit arithmetic operations `Arithmetic and jump instructions`_
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BPF_JMP 0x05 64-bit jump operations `Arithmetic and jump instructions`_
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BPF_JMP32 0x06 32-bit jump operations `Arithmetic and jump instructions`_
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BPF_ALU64 0x07 64-bit arithmetic operations `Arithmetic and jump instructions`_
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========= ===== =============================== ===================================
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Arithmetic and jump instructions
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================================
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For arithmetic and jump instructions (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` and
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``BPF_JMP32``), the 8-bit 'opcode' field is divided into three parts:
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============== ====== =================
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4 bits (MSB) 1 bit 3 bits (LSB)
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============== ====== =================
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code source instruction class
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============== ====== =================
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**code**
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the operation code, whose meaning varies by instruction class
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**source**
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the source operand location, which unless otherwise specified is one of:
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====== ===== ==============================================
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source value description
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====== ===== ==============================================
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BPF_K 0x00 use 32-bit 'imm' value as source operand
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BPF_X 0x08 use 'src_reg' register value as source operand
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====== ===== ==============================================
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**instruction class**
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the instruction class (see `Instruction classes`_)
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Arithmetic instructions
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-----------------------
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``BPF_ALU`` uses 32-bit wide operands while ``BPF_ALU64`` uses 64-bit wide operands for
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otherwise identical operations.
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The 'code' field encodes the operation as below, where 'src' and 'dst' refer
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to the values of the source and destination registers, respectively.
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======== ===== ==========================================================
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code value description
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======== ===== ==========================================================
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BPF_ADD 0x00 dst += src
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BPF_SUB 0x10 dst -= src
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BPF_MUL 0x20 dst \*= src
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BPF_DIV 0x30 dst = (src != 0) ? (dst / src) : 0
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BPF_OR 0x40 dst \|= src
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BPF_AND 0x50 dst &= src
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BPF_LSH 0x60 dst <<= src
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BPF_RSH 0x70 dst >>= src
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BPF_NEG 0x80 dst = ~src
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BPF_MOD 0x90 dst = (src != 0) ? (dst % src) : dst
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BPF_XOR 0xa0 dst ^= src
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BPF_MOV 0xb0 dst = src
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BPF_ARSH 0xc0 sign extending shift right
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BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below)
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======== ===== ==========================================================
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Underflow and overflow are allowed during arithmetic operations, meaning
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the 64-bit or 32-bit value will wrap. If eBPF program execution would
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result in division by zero, the destination register is instead set to zero.
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If execution would result in modulo by zero, for ``BPF_ALU64`` the value of
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the destination register is unchanged whereas for ``BPF_ALU`` the upper
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32 bits of the destination register are zeroed.
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``BPF_ADD | BPF_X | BPF_ALU`` means::
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dst = (u32) ((u32) dst + (u32) src)
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where '(u32)' indicates that the upper 32 bits are zeroed.
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``BPF_ADD | BPF_X | BPF_ALU64`` means::
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dst = dst + src
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``BPF_XOR | BPF_K | BPF_ALU`` means::
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dst = (u32) dst ^ (u32) imm32
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``BPF_XOR | BPF_K | BPF_ALU64`` means::
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dst = dst ^ imm32
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Also note that the division and modulo operations are unsigned. Thus, for
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``BPF_ALU``, 'imm' is first interpreted as an unsigned 32-bit value, whereas
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for ``BPF_ALU64``, 'imm' is first sign extended to 64 bits and the result
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interpreted as an unsigned 64-bit value. There are no instructions for
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signed division or modulo.
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Byte swap instructions
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~~~~~~~~~~~~~~~~~~~~~~
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The byte swap instructions use an instruction class of ``BPF_ALU`` and a 4-bit
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'code' field of ``BPF_END``.
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The byte swap instructions operate on the destination register
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only and do not use a separate source register or immediate value.
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The 1-bit source operand field in the opcode is used to select what byte
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order the operation convert from or to:
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========= ===== =================================================
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source value description
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========= ===== =================================================
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BPF_TO_LE 0x00 convert between host byte order and little endian
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BPF_TO_BE 0x08 convert between host byte order and big endian
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========= ===== =================================================
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The 'imm' field encodes the width of the swap operations. The following widths
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are supported: 16, 32 and 64.
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Examples:
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``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16 means::
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dst = htole16(dst)
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``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 64 means::
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dst = htobe64(dst)
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Jump instructions
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-----------------
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``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for
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otherwise identical operations.
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The 'code' field encodes the operation as below:
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======== ===== === =========================================== =========================================
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code value src description notes
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======== ===== === =========================================== =========================================
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BPF_JA 0x0 0x0 PC += offset BPF_JMP only
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BPF_JEQ 0x1 any PC += offset if dst == src
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BPF_JGT 0x2 any PC += offset if dst > src unsigned
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BPF_JGE 0x3 any PC += offset if dst >= src unsigned
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BPF_JSET 0x4 any PC += offset if dst & src
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BPF_JNE 0x5 any PC += offset if dst != src
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BPF_JSGT 0x6 any PC += offset if dst > src signed
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BPF_JSGE 0x7 any PC += offset if dst >= src signed
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BPF_CALL 0x8 0x0 call helper function by address see `Helper functions`_
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BPF_CALL 0x8 0x1 call PC += offset see `Program-local functions`_
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BPF_CALL 0x8 0x2 call helper function by BTF ID see `Helper functions`_
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BPF_EXIT 0x9 0x0 return BPF_JMP only
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BPF_JLT 0xa any PC += offset if dst < src unsigned
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BPF_JLE 0xb any PC += offset if dst <= src unsigned
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BPF_JSLT 0xc any PC += offset if dst < src signed
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BPF_JSLE 0xd any PC += offset if dst <= src signed
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======== ===== === =========================================== =========================================
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The eBPF program needs to store the return value into register R0 before doing a
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``BPF_EXIT``.
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Example:
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``BPF_JSGE | BPF_X | BPF_JMP32`` (0x7e) means::
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if (s32)dst s>= (s32)src goto +offset
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where 's>=' indicates a signed '>=' comparison.
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Helper functions
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~~~~~~~~~~~~~~~~
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Helper functions are a concept whereby BPF programs can call into a
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set of function calls exposed by the underlying platform.
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Historically, each helper function was identified by an address
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encoded in the imm field. The available helper functions may differ
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for each program type, but address values are unique across all program types.
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Platforms that support the BPF Type Format (BTF) support identifying
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a helper function by a BTF ID encoded in the imm field, where the BTF ID
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identifies the helper name and type.
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Program-local functions
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~~~~~~~~~~~~~~~~~~~~~~~
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Program-local functions are functions exposed by the same BPF program as the
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caller, and are referenced by offset from the call instruction, similar to
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``BPF_JA``. A ``BPF_EXIT`` within the program-local function will return to
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the caller.
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Load and store instructions
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===========================
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For load and store instructions (``BPF_LD``, ``BPF_LDX``, ``BPF_ST``, and ``BPF_STX``), the
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8-bit 'opcode' field is divided as:
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============ ====== =================
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3 bits (MSB) 2 bits 3 bits (LSB)
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============ ====== =================
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mode size instruction class
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============ ====== =================
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The mode modifier is one of:
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============= ===== ==================================== =============
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mode modifier value description reference
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============= ===== ==================================== =============
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BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_
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BPF_ABS 0x20 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_
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BPF_IND 0x40 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_
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BPF_MEM 0x60 regular load and store operations `Regular load and store operations`_
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BPF_ATOMIC 0xc0 atomic operations `Atomic operations`_
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============= ===== ==================================== =============
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The size modifier is one of:
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============= ===== =====================
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size modifier value description
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============= ===== =====================
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BPF_W 0x00 word (4 bytes)
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BPF_H 0x08 half word (2 bytes)
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BPF_B 0x10 byte
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BPF_DW 0x18 double word (8 bytes)
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============= ===== =====================
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Regular load and store operations
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---------------------------------
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The ``BPF_MEM`` mode modifier is used to encode regular load and store
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instructions that transfer data between a register and memory.
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``BPF_MEM | <size> | BPF_STX`` means::
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*(size *) (dst + offset) = src
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``BPF_MEM | <size> | BPF_ST`` means::
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*(size *) (dst + offset) = imm32
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``BPF_MEM | <size> | BPF_LDX`` means::
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dst = *(size *) (src + offset)
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Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``.
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Atomic operations
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-----------------
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Atomic operations are operations that operate on memory and can not be
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interrupted or corrupted by other access to the same memory region
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by other eBPF programs or means outside of this specification.
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All atomic operations supported by eBPF are encoded as store operations
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that use the ``BPF_ATOMIC`` mode modifier as follows:
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* ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations
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* ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations
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* 8-bit and 16-bit wide atomic operations are not supported.
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The 'imm' field is used to encode the actual atomic operation.
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Simple atomic operation use a subset of the values defined to encode
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arithmetic operations in the 'imm' field to encode the atomic operation:
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======== ===== ===========
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imm value description
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======== ===== ===========
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BPF_ADD 0x00 atomic add
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BPF_OR 0x40 atomic or
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BPF_AND 0x50 atomic and
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BPF_XOR 0xa0 atomic xor
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======== ===== ===========
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``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means::
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*(u32 *)(dst + offset) += src
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``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means::
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*(u64 *)(dst + offset) += src
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In addition to the simple atomic operations, there also is a modifier and
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two complex atomic operations:
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=========== ================ ===========================
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imm value description
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=========== ================ ===========================
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BPF_FETCH 0x01 modifier: return old value
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BPF_XCHG 0xe0 | BPF_FETCH atomic exchange
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BPF_CMPXCHG 0xf0 | BPF_FETCH atomic compare and exchange
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=========== ================ ===========================
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The ``BPF_FETCH`` modifier is optional for simple atomic operations, and
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always set for the complex atomic operations. If the ``BPF_FETCH`` flag
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is set, then the operation also overwrites ``src`` with the value that
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was in memory before it was modified.
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The ``BPF_XCHG`` operation atomically exchanges ``src`` with the value
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addressed by ``dst + offset``.
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The ``BPF_CMPXCHG`` operation atomically compares the value addressed by
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``dst + offset`` with ``R0``. If they match, the value addressed by
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``dst + offset`` is replaced with ``src``. In either case, the
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value that was at ``dst + offset`` before the operation is zero-extended
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and loaded back to ``R0``.
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64-bit immediate instructions
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-----------------------------
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Instructions with the ``BPF_IMM`` 'mode' modifier use the wide instruction
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encoding defined in `Instruction encoding`_, and use the 'src' field of the
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basic instruction to hold an opcode subtype.
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The following table defines a set of ``BPF_IMM | BPF_DW | BPF_LD`` instructions
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with opcode subtypes in the 'src' field, using new terms such as "map"
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defined further below:
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========================= ====== === ========================================= =========== ==============
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opcode construction opcode src pseudocode imm type dst type
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========================= ====== === ========================================= =========== ==============
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BPF_IMM | BPF_DW | BPF_LD 0x18 0x0 dst = imm64 integer integer
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BPF_IMM | BPF_DW | BPF_LD 0x18 0x1 dst = map_by_fd(imm) map fd map
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BPF_IMM | BPF_DW | BPF_LD 0x18 0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data pointer
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BPF_IMM | BPF_DW | BPF_LD 0x18 0x3 dst = var_addr(imm) variable id data pointer
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BPF_IMM | BPF_DW | BPF_LD 0x18 0x4 dst = code_addr(imm) integer code pointer
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BPF_IMM | BPF_DW | BPF_LD 0x18 0x5 dst = map_by_idx(imm) map index map
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BPF_IMM | BPF_DW | BPF_LD 0x18 0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data pointer
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========================= ====== === ========================================= =========== ==============
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where
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* map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_)
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* map_by_idx(imm) means to convert a 32-bit index into an address of a map
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* map_val(map) gets the address of the first value in a given map
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* var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id
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* code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions
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* the 'imm type' can be used by disassemblers for display
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* the 'dst type' can be used for verification and JIT compilation purposes
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Maps
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~~~~
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Maps are shared memory regions accessible by eBPF programs on some platforms.
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A map can have various semantics as defined in a separate document, and may or
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may not have a single contiguous memory region, but the 'map_val(map)' is
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currently only defined for maps that do have a single contiguous memory region.
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Each map can have a file descriptor (fd) if supported by the platform, where
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'map_by_fd(imm)' means to get the map with the specified file descriptor. Each
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BPF program can also be defined to use a set of maps associated with the
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program at load time, and 'map_by_idx(imm)' means to get the map with the given
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index in the set associated with the BPF program containing the instruction.
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Platform Variables
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~~~~~~~~~~~~~~~~~~
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Platform variables are memory regions, identified by integer ids, exposed by
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the runtime and accessible by BPF programs on some platforms. The
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'var_addr(imm)' operation means to get the address of the memory region
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identified by the given id.
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Legacy BPF Packet access instructions
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-------------------------------------
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eBPF previously introduced special instructions for access to packet data that were
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carried over from classic BPF. However, these instructions are
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deprecated and should no longer be used.
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