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b1b6802586
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
629 lines
14 KiB
Plaintext
629 lines
14 KiB
Plaintext
/*
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* MPC8641 HPCN Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "MPC8641HPCN";
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compatible = "fsl,mpc8641hpcn";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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/*
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* Only one of Rapid IO or PCI can be present due to HW limitations and
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* due to the fact that the 2 now share address space in the new memory
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* map. The most likely case is that we have PCI, so comment out the
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* rapidio node. Leave it here for reference.
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*/
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/* rapidio0 = &rapidio0; */
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8641@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>; // L1
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i-cache-size = <32768>; // L1
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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PowerPC,8641@1 {
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device_type = "cpu";
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reg = <1>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; // 1G at 0x0
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};
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localbus@ffe05000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-localbus", "simple-bus";
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reg = <0xffe05000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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ranges = <0 0 0xef800000 0x00800000
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2 0 0xffdf8000 0x00008000
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3 0 0xffdf0000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x00800000>;
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bank-width = <2>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00300000>;
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};
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partition@300000 {
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label = "firmware b";
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reg = <0x00300000 0x00100000>;
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read-only;
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};
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partition@400000 {
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label = "fs";
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reg = <0x00400000 0x00300000>;
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};
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partition@700000 {
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label = "firmware a";
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reg = <0x00700000 0x00100000>;
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read-only;
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};
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};
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};
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soc8641@ffe00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x00000000 0xffe00000 0x00100000>;
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bus-frequency = <0>;
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mcm-law@0 {
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compatible = "fsl,mcm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <10>;
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};
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mcm@1000 {
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compatible = "fsl,mpc8641-mcm", "fsl,mcm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet2: ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <2>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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ranges = <0x0 0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet3: ethernet@27000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <3>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x27000 0x1000>;
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ranges = <0x0 0x27000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <37 2 38 2 39 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <28 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8641-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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pci0: pcie@ffe08000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xffe08000 0x1000>;
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bus-range = <0x0 0xff>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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interrupt-map-mask = <0xff00 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 func 0 - PCI slot 1 */
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0x8800 0 0 1 &mpic 2 1
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0x8800 0 0 2 &mpic 3 1
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0x8800 0 0 3 &mpic 4 1
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0x8800 0 0 4 &mpic 1 1
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/* IDSEL 0x11 func 1 - PCI slot 1 */
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0x8900 0 0 1 &mpic 2 1
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0x8900 0 0 2 &mpic 3 1
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0x8900 0 0 3 &mpic 4 1
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0x8900 0 0 4 &mpic 1 1
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/* IDSEL 0x11 func 2 - PCI slot 1 */
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0x8a00 0 0 1 &mpic 2 1
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0x8a00 0 0 2 &mpic 3 1
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0x8a00 0 0 3 &mpic 4 1
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0x8a00 0 0 4 &mpic 1 1
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/* IDSEL 0x11 func 3 - PCI slot 1 */
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0x8b00 0 0 1 &mpic 2 1
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0x8b00 0 0 2 &mpic 3 1
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0x8b00 0 0 3 &mpic 4 1
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0x8b00 0 0 4 &mpic 1 1
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/* IDSEL 0x11 func 4 - PCI slot 1 */
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0x8c00 0 0 1 &mpic 2 1
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0x8c00 0 0 2 &mpic 3 1
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0x8c00 0 0 3 &mpic 4 1
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0x8c00 0 0 4 &mpic 1 1
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/* IDSEL 0x11 func 5 - PCI slot 1 */
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0x8d00 0 0 1 &mpic 2 1
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0x8d00 0 0 2 &mpic 3 1
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0x8d00 0 0 3 &mpic 4 1
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0x8d00 0 0 4 &mpic 1 1
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/* IDSEL 0x11 func 6 - PCI slot 1 */
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0x8e00 0 0 1 &mpic 2 1
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0x8e00 0 0 2 &mpic 3 1
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0x8e00 0 0 3 &mpic 4 1
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0x8e00 0 0 4 &mpic 1 1
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/* IDSEL 0x11 func 7 - PCI slot 1 */
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0x8f00 0 0 1 &mpic 2 1
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0x8f00 0 0 2 &mpic 3 1
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0x8f00 0 0 3 &mpic 4 1
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0x8f00 0 0 4 &mpic 1 1
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/* IDSEL 0x12 func 0 - PCI slot 2 */
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0x9000 0 0 1 &mpic 3 1
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0x9000 0 0 2 &mpic 4 1
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0x9000 0 0 3 &mpic 1 1
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0x9000 0 0 4 &mpic 2 1
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/* IDSEL 0x12 func 1 - PCI slot 2 */
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0x9100 0 0 1 &mpic 3 1
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0x9100 0 0 2 &mpic 4 1
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0x9100 0 0 3 &mpic 1 1
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0x9100 0 0 4 &mpic 2 1
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/* IDSEL 0x12 func 2 - PCI slot 2 */
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0x9200 0 0 1 &mpic 3 1
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0x9200 0 0 2 &mpic 4 1
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0x9200 0 0 3 &mpic 1 1
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0x9200 0 0 4 &mpic 2 1
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/* IDSEL 0x12 func 3 - PCI slot 2 */
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0x9300 0 0 1 &mpic 3 1
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0x9300 0 0 2 &mpic 4 1
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0x9300 0 0 3 &mpic 1 1
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0x9300 0 0 4 &mpic 2 1
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/* IDSEL 0x12 func 4 - PCI slot 2 */
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0x9400 0 0 1 &mpic 3 1
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0x9400 0 0 2 &mpic 4 1
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0x9400 0 0 3 &mpic 1 1
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0x9400 0 0 4 &mpic 2 1
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/* IDSEL 0x12 func 5 - PCI slot 2 */
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0x9500 0 0 1 &mpic 3 1
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0x9500 0 0 2 &mpic 4 1
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0x9500 0 0 3 &mpic 1 1
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0x9500 0 0 4 &mpic 2 1
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/* IDSEL 0x12 func 6 - PCI slot 2 */
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0x9600 0 0 1 &mpic 3 1
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0x9600 0 0 2 &mpic 4 1
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0x9600 0 0 3 &mpic 1 1
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0x9600 0 0 4 &mpic 2 1
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/* IDSEL 0x12 func 7 - PCI slot 2 */
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0x9700 0 0 1 &mpic 3 1
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0x9700 0 0 2 &mpic 4 1
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0x9700 0 0 3 &mpic 1 1
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0x9700 0 0 4 &mpic 2 1
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// IDSEL 0x1c USB
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0xe000 0 0 1 &i8259 12 2
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0xe100 0 0 2 &i8259 9 2
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0xe200 0 0 3 &i8259 10 2
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0xe300 0 0 4 &i8259 11 2
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// IDSEL 0x1d Audio
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0xe800 0 0 1 &i8259 6 2
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// IDSEL 0x1e Legacy
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0xf000 0 0 1 &i8259 7 2
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0xf100 0 0 1 &i8259 7 2
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// IDSEL 0x1f IDE/SATA
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0xf800 0 0 1 &i8259 14 2
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0xf900 0 0 1 &i8259 5 2
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
|
|
ranges = <0x02000000 0x0 0x80000000
|
|
0x02000000 0x0 0x80000000
|
|
0x0 0x20000000
|
|
|
|
0x01000000 0x0 0x00000000
|
|
0x01000000 0x0 0x00000000
|
|
0x0 0x00010000>;
|
|
uli1575@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
ranges = <0x02000000 0x0 0x80000000
|
|
0x02000000 0x0 0x80000000
|
|
0x0 0x20000000
|
|
0x01000000 0x0 0x00000000
|
|
0x01000000 0x0 0x00000000
|
|
0x0 0x00010000>;
|
|
isa@1e {
|
|
device_type = "isa";
|
|
#interrupt-cells = <2>;
|
|
#size-cells = <1>;
|
|
#address-cells = <2>;
|
|
reg = <0xf000 0 0 0 0>;
|
|
ranges = <1 0 0x01000000 0 0
|
|
0x00001000>;
|
|
interrupt-parent = <&i8259>;
|
|
|
|
i8259: interrupt-controller@20 {
|
|
reg = <1 0x20 2
|
|
1 0xa0 2
|
|
1 0x4d0 2>;
|
|
interrupt-controller;
|
|
device_type = "interrupt-controller";
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
compatible = "chrp,iic";
|
|
interrupts = <9 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
i8042@60 {
|
|
#size-cells = <0>;
|
|
#address-cells = <1>;
|
|
reg = <1 0x60 1 1 0x64 1>;
|
|
interrupts = <1 3 12 3>;
|
|
interrupt-parent =
|
|
<&i8259>;
|
|
|
|
keyboard@0 {
|
|
reg = <0>;
|
|
compatible = "pnpPNP,303";
|
|
};
|
|
|
|
mouse@1 {
|
|
reg = <1>;
|
|
compatible = "pnpPNP,f03";
|
|
};
|
|
};
|
|
|
|
rtc@70 {
|
|
compatible =
|
|
"pnpPNP,b00";
|
|
reg = <1 0x70 2>;
|
|
};
|
|
|
|
gpio@400 {
|
|
reg = <1 0x400 0x80>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
pci1: pcie@ffe09000 {
|
|
compatible = "fsl,mpc8641-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xffe09000 0x1000>;
|
|
bus-range = <0 0xff>;
|
|
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
|
|
0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <25 2>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0x0000 0 0 1 &mpic 4 1
|
|
0x0000 0 0 2 &mpic 5 1
|
|
0x0000 0 0 3 &mpic 6 1
|
|
0x0000 0 0 4 &mpic 7 1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x02000000 0x0 0xa0000000
|
|
0x02000000 0x0 0xa0000000
|
|
0x0 0x20000000
|
|
|
|
0x01000000 0x0 0x00000000
|
|
0x01000000 0x0 0x00000000
|
|
0x0 0x00010000>;
|
|
};
|
|
};
|
|
/*
|
|
rapidio0: rapidio@ffec0000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "fsl,rapidio-delta";
|
|
reg = <0xffec0000 0x20000>;
|
|
ranges = <0 0 0x80000000 0 0x20000000>;
|
|
interrupt-parent = <&mpic>;
|
|
// err_irq bell_outb_irq bell_inb_irq
|
|
// msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq
|
|
interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;
|
|
};
|
|
*/
|
|
|
|
};
|