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24921dbd29
The PECI CPU sensors are available as soon as the CPU is powered, however the PECI DIMM sensors are available after DRAM has been trained and thresholds have been written by host firmware. The default timeout of 30 seconds isn't enough for modern multisocket platforms utilizing DDR5 memory to bring up the memory and enable PECI sensor data. Bump the default timeout to 10 minutes in case the system starts without cached DDR5 training data. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231130090422.2535542-1-patrick.rudolph@9elements.com [groeck: List affected driver in patch subject] Signed-off-by: Guenter Roeck <linux@roeck-us.net>
670 lines
18 KiB
C
670 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2018-2021 Intel Corporation
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#include <linux/auxiliary_bus.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/devm-helpers.h>
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#include <linux/hwmon.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/peci.h>
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#include <linux/peci-cpu.h>
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#include <linux/units.h>
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#include <linux/workqueue.h>
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#include "common.h"
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#define DIMM_MASK_CHECK_DELAY_JIFFIES msecs_to_jiffies(5000)
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/* Max number of channel ranks and DIMM index per channel */
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#define CHAN_RANK_MAX_ON_HSX 8
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#define DIMM_IDX_MAX_ON_HSX 3
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#define CHAN_RANK_MAX_ON_BDX 4
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#define DIMM_IDX_MAX_ON_BDX 3
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#define CHAN_RANK_MAX_ON_BDXD 2
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#define DIMM_IDX_MAX_ON_BDXD 2
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#define CHAN_RANK_MAX_ON_SKX 6
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#define DIMM_IDX_MAX_ON_SKX 2
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#define CHAN_RANK_MAX_ON_ICX 8
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#define DIMM_IDX_MAX_ON_ICX 2
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#define CHAN_RANK_MAX_ON_ICXD 4
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#define DIMM_IDX_MAX_ON_ICXD 2
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#define CHAN_RANK_MAX_ON_SPR 8
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#define DIMM_IDX_MAX_ON_SPR 2
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#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
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#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
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#define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX)
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#define CPU_SEG_MASK GENMASK(23, 16)
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#define GET_CPU_SEG(x) (((x) & CPU_SEG_MASK) >> 16)
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#define CPU_BUS_MASK GENMASK(7, 0)
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#define GET_CPU_BUS(x) ((x) & CPU_BUS_MASK)
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#define DIMM_TEMP_MAX GENMASK(15, 8)
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#define DIMM_TEMP_CRIT GENMASK(23, 16)
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#define GET_TEMP_MAX(x) (((x) & DIMM_TEMP_MAX) >> 8)
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#define GET_TEMP_CRIT(x) (((x) & DIMM_TEMP_CRIT) >> 16)
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#define NO_DIMM_RETRY_COUNT_MAX 120
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struct peci_dimmtemp;
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struct dimm_info {
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int chan_rank_max;
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int dimm_idx_max;
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u8 min_peci_revision;
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int (*read_thresholds)(struct peci_dimmtemp *priv, int dimm_order,
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int chan_rank, u32 *data);
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};
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struct peci_dimm_thresholds {
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long temp_max;
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long temp_crit;
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struct peci_sensor_state state;
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};
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enum peci_dimm_threshold_type {
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temp_max_type,
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temp_crit_type,
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};
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struct peci_dimmtemp {
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struct peci_device *peci_dev;
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struct device *dev;
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const char *name;
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const struct dimm_info *gen_info;
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struct delayed_work detect_work;
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struct {
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struct peci_sensor_data temp;
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struct peci_dimm_thresholds thresholds;
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} dimm[DIMM_NUMS_MAX];
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char **dimmtemp_label;
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DECLARE_BITMAP(dimm_mask, DIMM_NUMS_MAX);
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u8 no_dimm_retry_count;
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};
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static u8 __dimm_temp(u32 reg, int dimm_order)
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{
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return (reg >> (dimm_order * 8)) & 0xff;
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}
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static int get_dimm_temp(struct peci_dimmtemp *priv, int dimm_no, long *val)
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{
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int dimm_order = dimm_no % priv->gen_info->dimm_idx_max;
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int chan_rank = dimm_no / priv->gen_info->dimm_idx_max;
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int ret = 0;
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u32 data;
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mutex_lock(&priv->dimm[dimm_no].temp.state.lock);
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if (!peci_sensor_need_update(&priv->dimm[dimm_no].temp.state))
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goto skip_update;
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ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &data);
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if (ret)
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goto unlock;
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priv->dimm[dimm_no].temp.value = __dimm_temp(data, dimm_order) * MILLIDEGREE_PER_DEGREE;
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peci_sensor_mark_updated(&priv->dimm[dimm_no].temp.state);
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skip_update:
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*val = priv->dimm[dimm_no].temp.value;
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unlock:
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mutex_unlock(&priv->dimm[dimm_no].temp.state.lock);
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return ret;
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}
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static int update_thresholds(struct peci_dimmtemp *priv, int dimm_no)
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{
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int dimm_order = dimm_no % priv->gen_info->dimm_idx_max;
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int chan_rank = dimm_no / priv->gen_info->dimm_idx_max;
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u32 data;
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int ret;
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if (!peci_sensor_need_update(&priv->dimm[dimm_no].thresholds.state))
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return 0;
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ret = priv->gen_info->read_thresholds(priv, dimm_order, chan_rank, &data);
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if (ret == -ENODATA) /* Use default or previous value */
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return 0;
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if (ret)
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return ret;
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priv->dimm[dimm_no].thresholds.temp_max = GET_TEMP_MAX(data) * MILLIDEGREE_PER_DEGREE;
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priv->dimm[dimm_no].thresholds.temp_crit = GET_TEMP_CRIT(data) * MILLIDEGREE_PER_DEGREE;
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peci_sensor_mark_updated(&priv->dimm[dimm_no].thresholds.state);
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return 0;
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}
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static int get_dimm_thresholds(struct peci_dimmtemp *priv, enum peci_dimm_threshold_type type,
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int dimm_no, long *val)
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{
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int ret;
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mutex_lock(&priv->dimm[dimm_no].thresholds.state.lock);
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ret = update_thresholds(priv, dimm_no);
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if (ret)
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goto unlock;
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switch (type) {
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case temp_max_type:
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*val = priv->dimm[dimm_no].thresholds.temp_max;
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break;
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case temp_crit_type:
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*val = priv->dimm[dimm_no].thresholds.temp_crit;
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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unlock:
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mutex_unlock(&priv->dimm[dimm_no].thresholds.state.lock);
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return ret;
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}
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static int dimmtemp_read_string(struct device *dev,
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enum hwmon_sensor_types type,
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u32 attr, int channel, const char **str)
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{
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struct peci_dimmtemp *priv = dev_get_drvdata(dev);
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if (attr != hwmon_temp_label)
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return -EOPNOTSUPP;
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*str = (const char *)priv->dimmtemp_label[channel];
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return 0;
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}
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static int dimmtemp_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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struct peci_dimmtemp *priv = dev_get_drvdata(dev);
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switch (attr) {
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case hwmon_temp_input:
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return get_dimm_temp(priv, channel, val);
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case hwmon_temp_max:
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return get_dimm_thresholds(priv, temp_max_type, channel, val);
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case hwmon_temp_crit:
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return get_dimm_thresholds(priv, temp_crit_type, channel, val);
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default:
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break;
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}
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return -EOPNOTSUPP;
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}
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static umode_t dimmtemp_is_visible(const void *data, enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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const struct peci_dimmtemp *priv = data;
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if (test_bit(channel, priv->dimm_mask))
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return 0444;
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return 0;
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}
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static const struct hwmon_ops peci_dimmtemp_ops = {
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.is_visible = dimmtemp_is_visible,
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.read_string = dimmtemp_read_string,
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.read = dimmtemp_read,
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};
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static int check_populated_dimms(struct peci_dimmtemp *priv)
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{
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int chan_rank_max = priv->gen_info->chan_rank_max;
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int dimm_idx_max = priv->gen_info->dimm_idx_max;
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DECLARE_BITMAP(dimm_mask, DIMM_NUMS_MAX);
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DECLARE_BITMAP(chan_rank_empty, CHAN_RANK_MAX);
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int chan_rank, dimm_idx, ret, i;
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u32 pcs;
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if (chan_rank_max * dimm_idx_max > DIMM_NUMS_MAX) {
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WARN_ONCE(1, "Unsupported number of DIMMs - chan_rank_max: %d, dimm_idx_max: %d",
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chan_rank_max, dimm_idx_max);
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return -EINVAL;
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}
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bitmap_zero(dimm_mask, DIMM_NUMS_MAX);
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bitmap_zero(chan_rank_empty, CHAN_RANK_MAX);
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for (chan_rank = 0; chan_rank < chan_rank_max; chan_rank++) {
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ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &pcs);
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if (ret) {
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/*
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* Overall, we expect either success or -EINVAL in
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* order to determine whether DIMM is populated or not.
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* For anything else we fall back to deferring the
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* detection to be performed at a later point in time.
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*/
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if (ret == -EINVAL) {
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bitmap_set(chan_rank_empty, chan_rank, 1);
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continue;
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}
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return -EAGAIN;
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}
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for (dimm_idx = 0; dimm_idx < dimm_idx_max; dimm_idx++)
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if (__dimm_temp(pcs, dimm_idx))
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bitmap_set(dimm_mask, chan_rank * dimm_idx_max + dimm_idx, 1);
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}
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/*
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* If we got all -EINVALs, it means that the CPU doesn't have any
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* DIMMs. Unfortunately, it may also happen at the very start of
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* host platform boot. Retrying a couple of times lets us make sure
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* that the state is persistent.
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*/
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if (bitmap_full(chan_rank_empty, chan_rank_max)) {
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if (priv->no_dimm_retry_count < NO_DIMM_RETRY_COUNT_MAX) {
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priv->no_dimm_retry_count++;
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return -EAGAIN;
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}
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return -ENODEV;
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}
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/*
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* It's possible that memory training is not done yet. In this case we
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* defer the detection to be performed at a later point in time.
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*/
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if (bitmap_empty(dimm_mask, DIMM_NUMS_MAX)) {
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priv->no_dimm_retry_count = 0;
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return -EAGAIN;
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}
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for_each_set_bit(i, dimm_mask, DIMM_NUMS_MAX) {
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dev_dbg(priv->dev, "Found DIMM%#x\n", i);
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}
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bitmap_copy(priv->dimm_mask, dimm_mask, DIMM_NUMS_MAX);
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return 0;
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}
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static int create_dimm_temp_label(struct peci_dimmtemp *priv, int chan)
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{
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int rank = chan / priv->gen_info->dimm_idx_max;
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int idx = chan % priv->gen_info->dimm_idx_max;
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priv->dimmtemp_label[chan] = devm_kasprintf(priv->dev, GFP_KERNEL,
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"DIMM %c%d", 'A' + rank,
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idx + 1);
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if (!priv->dimmtemp_label[chan])
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return -ENOMEM;
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return 0;
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}
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static const struct hwmon_channel_info * const peci_dimmtemp_temp_info[] = {
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HWMON_CHANNEL_INFO(temp,
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[0 ... DIMM_NUMS_MAX - 1] = HWMON_T_LABEL |
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HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT),
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NULL
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};
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static const struct hwmon_chip_info peci_dimmtemp_chip_info = {
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.ops = &peci_dimmtemp_ops,
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.info = peci_dimmtemp_temp_info,
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};
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static int create_dimm_temp_info(struct peci_dimmtemp *priv)
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{
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int ret, i, channels;
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struct device *dev;
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/*
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* We expect to either find populated DIMMs and carry on with creating
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* sensors, or find out that there are no DIMMs populated.
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* All other states mean that the platform never reached the state that
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* allows to check DIMM state - causing us to retry later on.
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*/
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ret = check_populated_dimms(priv);
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if (ret == -ENODEV) {
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dev_dbg(priv->dev, "No DIMMs found\n");
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return 0;
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} else if (ret) {
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schedule_delayed_work(&priv->detect_work, DIMM_MASK_CHECK_DELAY_JIFFIES);
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dev_dbg(priv->dev, "Deferred populating DIMM temp info\n");
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return ret;
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}
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channels = priv->gen_info->chan_rank_max * priv->gen_info->dimm_idx_max;
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priv->dimmtemp_label = devm_kzalloc(priv->dev, channels * sizeof(char *), GFP_KERNEL);
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if (!priv->dimmtemp_label)
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return -ENOMEM;
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for_each_set_bit(i, priv->dimm_mask, DIMM_NUMS_MAX) {
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ret = create_dimm_temp_label(priv, i);
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if (ret)
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return ret;
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mutex_init(&priv->dimm[i].thresholds.state.lock);
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mutex_init(&priv->dimm[i].temp.state.lock);
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}
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dev = devm_hwmon_device_register_with_info(priv->dev, priv->name, priv,
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&peci_dimmtemp_chip_info, NULL);
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if (IS_ERR(dev)) {
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dev_err(priv->dev, "Failed to register hwmon device\n");
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return PTR_ERR(dev);
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}
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dev_dbg(priv->dev, "%s: sensor '%s'\n", dev_name(dev), priv->name);
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return 0;
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}
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static void create_dimm_temp_info_delayed(struct work_struct *work)
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{
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struct peci_dimmtemp *priv = container_of(to_delayed_work(work),
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struct peci_dimmtemp,
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detect_work);
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int ret;
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ret = create_dimm_temp_info(priv);
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if (ret && ret != -EAGAIN)
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dev_err(priv->dev, "Failed to populate DIMM temp info\n");
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}
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static int peci_dimmtemp_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
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{
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struct device *dev = &adev->dev;
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struct peci_device *peci_dev = to_peci_device(dev->parent);
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struct peci_dimmtemp *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->name = devm_kasprintf(dev, GFP_KERNEL, "peci_dimmtemp.cpu%d",
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peci_dev->info.socket_id);
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if (!priv->name)
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return -ENOMEM;
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priv->dev = dev;
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priv->peci_dev = peci_dev;
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priv->gen_info = (const struct dimm_info *)id->driver_data;
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/*
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* This is just a sanity check. Since we're using commands that are
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* guaranteed to be supported on a given platform, we should never see
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* revision lower than expected.
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*/
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if (peci_dev->info.peci_revision < priv->gen_info->min_peci_revision)
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dev_warn(priv->dev,
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"Unexpected PECI revision %#x, some features may be unavailable\n",
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peci_dev->info.peci_revision);
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ret = devm_delayed_work_autocancel(priv->dev, &priv->detect_work,
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create_dimm_temp_info_delayed);
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if (ret)
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return ret;
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ret = create_dimm_temp_info(priv);
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if (ret && ret != -EAGAIN) {
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dev_err(dev, "Failed to populate DIMM temp info\n");
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return ret;
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}
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return 0;
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}
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static int
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read_thresholds_hsx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
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{
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u8 dev, func;
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u16 reg;
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int ret;
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/*
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* Device 20, Function 0: IMC 0 channel 0 -> rank 0
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* Device 20, Function 1: IMC 0 channel 1 -> rank 1
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* Device 21, Function 0: IMC 0 channel 2 -> rank 2
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* Device 21, Function 1: IMC 0 channel 3 -> rank 3
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* Device 23, Function 0: IMC 1 channel 0 -> rank 4
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* Device 23, Function 1: IMC 1 channel 1 -> rank 5
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* Device 24, Function 0: IMC 1 channel 2 -> rank 6
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* Device 24, Function 1: IMC 1 channel 3 -> rank 7
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*/
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dev = 20 + chan_rank / 2 + chan_rank / 4;
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func = chan_rank % 2;
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reg = 0x120 + dimm_order * 4;
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ret = peci_pci_local_read(priv->peci_dev, 1, dev, func, reg, data);
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if (ret)
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return ret;
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return 0;
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}
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static int
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read_thresholds_bdxd(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
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{
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u8 dev, func;
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u16 reg;
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int ret;
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/*
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* Device 10, Function 2: IMC 0 channel 0 -> rank 0
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* Device 10, Function 6: IMC 0 channel 1 -> rank 1
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* Device 12, Function 2: IMC 1 channel 0 -> rank 2
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* Device 12, Function 6: IMC 1 channel 1 -> rank 3
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*/
|
|
dev = 10 + chan_rank / 2 * 2;
|
|
func = (chan_rank % 2) ? 6 : 2;
|
|
reg = 0x120 + dimm_order * 4;
|
|
|
|
ret = peci_pci_local_read(priv->peci_dev, 2, dev, func, reg, data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
read_thresholds_skx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
|
|
{
|
|
u8 dev, func;
|
|
u16 reg;
|
|
int ret;
|
|
|
|
/*
|
|
* Device 10, Function 2: IMC 0 channel 0 -> rank 0
|
|
* Device 10, Function 6: IMC 0 channel 1 -> rank 1
|
|
* Device 11, Function 2: IMC 0 channel 2 -> rank 2
|
|
* Device 12, Function 2: IMC 1 channel 0 -> rank 3
|
|
* Device 12, Function 6: IMC 1 channel 1 -> rank 4
|
|
* Device 13, Function 2: IMC 1 channel 2 -> rank 5
|
|
*/
|
|
dev = 10 + chan_rank / 3 * 2 + (chan_rank % 3 == 2 ? 1 : 0);
|
|
func = chan_rank % 3 == 1 ? 6 : 2;
|
|
reg = 0x120 + dimm_order * 4;
|
|
|
|
ret = peci_pci_local_read(priv->peci_dev, 2, dev, func, reg, data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
|
|
{
|
|
u32 reg_val;
|
|
u64 offset;
|
|
int ret;
|
|
u8 dev;
|
|
|
|
ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd4, ®_val);
|
|
if (ret || !(reg_val & BIT(31)))
|
|
return -ENODATA; /* Use default or previous value */
|
|
|
|
ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd0, ®_val);
|
|
if (ret)
|
|
return -ENODATA; /* Use default or previous value */
|
|
|
|
/*
|
|
* Device 26, Offset 224e0: IMC 0 channel 0 -> rank 0
|
|
* Device 26, Offset 264e0: IMC 0 channel 1 -> rank 1
|
|
* Device 27, Offset 224e0: IMC 1 channel 0 -> rank 2
|
|
* Device 27, Offset 264e0: IMC 1 channel 1 -> rank 3
|
|
* Device 28, Offset 224e0: IMC 2 channel 0 -> rank 4
|
|
* Device 28, Offset 264e0: IMC 2 channel 1 -> rank 5
|
|
* Device 29, Offset 224e0: IMC 3 channel 0 -> rank 6
|
|
* Device 29, Offset 264e0: IMC 3 channel 1 -> rank 7
|
|
*/
|
|
dev = 26 + chan_rank / 2;
|
|
offset = 0x224e0 + dimm_order * 4 + (chan_rank % 2) * 0x4000;
|
|
|
|
ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),
|
|
dev, 0, offset, data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
|
|
{
|
|
u32 reg_val;
|
|
u64 offset;
|
|
int ret;
|
|
u8 dev;
|
|
|
|
ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, ®_val);
|
|
if (ret || !(reg_val & BIT(31)))
|
|
return -ENODATA; /* Use default or previous value */
|
|
|
|
ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, ®_val);
|
|
if (ret)
|
|
return -ENODATA; /* Use default or previous value */
|
|
|
|
/*
|
|
* Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0
|
|
* Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1
|
|
* Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2
|
|
* Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3
|
|
* Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4
|
|
* Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5
|
|
* Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6
|
|
* Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7
|
|
*/
|
|
dev = 26 + chan_rank / 2;
|
|
offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000;
|
|
|
|
ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),
|
|
dev, 0, offset, data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dimm_info dimm_hsx = {
|
|
.chan_rank_max = CHAN_RANK_MAX_ON_HSX,
|
|
.dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
|
|
.min_peci_revision = 0x33,
|
|
.read_thresholds = &read_thresholds_hsx,
|
|
};
|
|
|
|
static const struct dimm_info dimm_bdx = {
|
|
.chan_rank_max = CHAN_RANK_MAX_ON_BDX,
|
|
.dimm_idx_max = DIMM_IDX_MAX_ON_BDX,
|
|
.min_peci_revision = 0x33,
|
|
.read_thresholds = &read_thresholds_hsx,
|
|
};
|
|
|
|
static const struct dimm_info dimm_bdxd = {
|
|
.chan_rank_max = CHAN_RANK_MAX_ON_BDXD,
|
|
.dimm_idx_max = DIMM_IDX_MAX_ON_BDXD,
|
|
.min_peci_revision = 0x33,
|
|
.read_thresholds = &read_thresholds_bdxd,
|
|
};
|
|
|
|
static const struct dimm_info dimm_skx = {
|
|
.chan_rank_max = CHAN_RANK_MAX_ON_SKX,
|
|
.dimm_idx_max = DIMM_IDX_MAX_ON_SKX,
|
|
.min_peci_revision = 0x33,
|
|
.read_thresholds = &read_thresholds_skx,
|
|
};
|
|
|
|
static const struct dimm_info dimm_icx = {
|
|
.chan_rank_max = CHAN_RANK_MAX_ON_ICX,
|
|
.dimm_idx_max = DIMM_IDX_MAX_ON_ICX,
|
|
.min_peci_revision = 0x40,
|
|
.read_thresholds = &read_thresholds_icx,
|
|
};
|
|
|
|
static const struct dimm_info dimm_icxd = {
|
|
.chan_rank_max = CHAN_RANK_MAX_ON_ICXD,
|
|
.dimm_idx_max = DIMM_IDX_MAX_ON_ICXD,
|
|
.min_peci_revision = 0x40,
|
|
.read_thresholds = &read_thresholds_icx,
|
|
};
|
|
|
|
static const struct dimm_info dimm_spr = {
|
|
.chan_rank_max = CHAN_RANK_MAX_ON_SPR,
|
|
.dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
|
|
.min_peci_revision = 0x40,
|
|
.read_thresholds = &read_thresholds_spr,
|
|
};
|
|
|
|
static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
|
|
{
|
|
.name = "peci_cpu.dimmtemp.hsx",
|
|
.driver_data = (kernel_ulong_t)&dimm_hsx,
|
|
},
|
|
{
|
|
.name = "peci_cpu.dimmtemp.bdx",
|
|
.driver_data = (kernel_ulong_t)&dimm_bdx,
|
|
},
|
|
{
|
|
.name = "peci_cpu.dimmtemp.bdxd",
|
|
.driver_data = (kernel_ulong_t)&dimm_bdxd,
|
|
},
|
|
{
|
|
.name = "peci_cpu.dimmtemp.skx",
|
|
.driver_data = (kernel_ulong_t)&dimm_skx,
|
|
},
|
|
{
|
|
.name = "peci_cpu.dimmtemp.icx",
|
|
.driver_data = (kernel_ulong_t)&dimm_icx,
|
|
},
|
|
{
|
|
.name = "peci_cpu.dimmtemp.icxd",
|
|
.driver_data = (kernel_ulong_t)&dimm_icxd,
|
|
},
|
|
{
|
|
.name = "peci_cpu.dimmtemp.spr",
|
|
.driver_data = (kernel_ulong_t)&dimm_spr,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
|
|
|
|
static struct auxiliary_driver peci_dimmtemp_driver = {
|
|
.probe = peci_dimmtemp_probe,
|
|
.id_table = peci_dimmtemp_ids,
|
|
};
|
|
|
|
module_auxiliary_driver(peci_dimmtemp_driver);
|
|
|
|
MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>");
|
|
MODULE_AUTHOR("Iwona Winiarska <iwona.winiarska@intel.com>");
|
|
MODULE_DESCRIPTION("PECI dimmtemp driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_IMPORT_NS(PECI_CPU);
|