linux/arch/powerpc/mm/pageattr.c
Christophe Leroy 65883b78bc powerpc: align address to page boundary in change_page_attr()
Aligning address to page boundary allows flush_tlb_kernel_range()
to know it's a single page flush and use tlbie instead of tlbia.

On 603 we now have the following code in first leg of
change_page_attr():

	  2c:	55 29 00 3c 	rlwinm  r9,r9,0,0,30
	  30:	91 23 00 00 	stw     r9,0(r3)
	  34:	7c 00 22 64 	tlbie   r4,r0
	  38:	7c 00 04 ac 	hwsync
	  3c:	38 60 00 00 	li      r3,0
	  40:	4e 80 00 20 	blr

Before we had:

	  28:	55 29 00 3c 	rlwinm  r9,r9,0,0,30
	  2c:	91 23 00 00 	stw     r9,0(r3)
	  30:	54 89 00 26 	rlwinm  r9,r4,0,0,19
	  34:	38 84 10 00 	addi    r4,r4,4096
	  38:	7c 89 20 50 	subf    r4,r9,r4
	  3c:	28 04 10 00 	cmplwi  r4,4096
	  40:	41 81 00 30 	bgt     70 <change_page_attr+0x70>
	  44:	7c 00 4a 64 	tlbie   r9,r0
	  48:	7c 00 04 ac 	hwsync
	  4c:	38 60 00 00 	li      r3,0
	  50:	4e 80 00 20 	blr
	...
	  70:	94 21 ff f0 	stwu    r1,-16(r1)
	  74:	7c 08 02 a6 	mflr    r0
	  78:	90 01 00 14 	stw     r0,20(r1)
	  7c:	48 00 00 01 	bl      7c <change_page_attr+0x7c>
				7c: R_PPC_REL24	_tlbia
	  80:	80 01 00 14 	lwz     r0,20(r1)
	  84:	38 60 00 00 	li      r3,0
	  88:	7c 08 03 a6 	mtlr    r0
	  8c:	38 21 00 10 	addi    r1,r1,16
	  90:	4e 80 00 20 	blr

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/6bb118fb2ee89fa3c1f9cf90ed19f88220002cb0.1647877467.git.christophe.leroy@csgroup.eu
2022-05-08 22:15:41 +10:00

100 lines
2.5 KiB
C

// SPDX-License-Identifier: GPL-2.0
/*
* MMU-generic set_memory implementation for powerpc
*
* Copyright 2019-2021, IBM Corporation.
*/
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/set_memory.h>
#include <asm/mmu.h>
#include <asm/page.h>
#include <asm/pgtable.h>
static pte_basic_t pte_update_delta(pte_t *ptep, unsigned long addr,
unsigned long old, unsigned long new)
{
return pte_update(&init_mm, addr, ptep, old & ~new, new & ~old, 0);
}
/*
* Updates the attributes of a page atomically.
*
* This sequence is safe against concurrent updates, and also allows updating the
* attributes of a page currently being executed or accessed.
*/
static int change_page_attr(pte_t *ptep, unsigned long addr, void *data)
{
long action = (long)data;
addr &= PAGE_MASK;
/* modify the PTE bits as desired */
switch (action) {
case SET_MEMORY_RO:
/* Don't clear DIRTY bit */
pte_update_delta(ptep, addr, _PAGE_KERNEL_RW & ~_PAGE_DIRTY, _PAGE_KERNEL_RO);
break;
case SET_MEMORY_RW:
pte_update_delta(ptep, addr, _PAGE_KERNEL_RO, _PAGE_KERNEL_RW);
break;
case SET_MEMORY_NX:
pte_update_delta(ptep, addr, _PAGE_KERNEL_ROX, _PAGE_KERNEL_RO);
break;
case SET_MEMORY_X:
pte_update_delta(ptep, addr, _PAGE_KERNEL_RO, _PAGE_KERNEL_ROX);
break;
case SET_MEMORY_NP:
pte_update(&init_mm, addr, ptep, _PAGE_PRESENT, 0, 0);
break;
case SET_MEMORY_P:
pte_update(&init_mm, addr, ptep, 0, _PAGE_PRESENT, 0);
break;
default:
WARN_ON_ONCE(1);
break;
}
/* See ptesync comment in radix__set_pte_at() */
if (radix_enabled())
asm volatile("ptesync": : :"memory");
flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
return 0;
}
int change_memory_attr(unsigned long addr, int numpages, long action)
{
unsigned long start = ALIGN_DOWN(addr, PAGE_SIZE);
unsigned long size = numpages * PAGE_SIZE;
if (!numpages)
return 0;
if (WARN_ON_ONCE(is_vmalloc_or_module_addr((void *)addr) &&
is_vm_area_hugepages((void *)addr)))
return -EINVAL;
#ifdef CONFIG_PPC_BOOK3S_64
/*
* On hash, the linear mapping is not in the Linux page table so
* apply_to_existing_page_range() will have no effect. If in the future
* the set_memory_* functions are used on the linear map this will need
* to be updated.
*/
if (!radix_enabled()) {
int region = get_region_id(addr);
if (WARN_ON_ONCE(region != VMALLOC_REGION_ID && region != IO_REGION_ID))
return -EINVAL;
}
#endif
return apply_to_existing_page_range(&init_mm, start, size,
change_page_attr, (void *)action);
}