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e79f49c37c
Based on our observations, after any vm-exit associated with vPMU, there are at least two or more perf interfaces to be called for guest counter emulation, such as perf_event_{pause, read_value, period}(), and each one will {lock, unlock} the same perf_event_ctx. The frequency of calls becomes more severe when guest use counters in a multiplexed manner. Holding a lock once and completing the KVM request operations in the perf context would introduce a set of impractical new interfaces. So we can further optimize the vPMU implementation by avoiding repeated calls to these interfaces in the KVM context for at least one pattern: After we call perf_event_pause() once, the event will be disabled and its internal count will be reset to 0. So there is no need to pause it again or read its value. Once the event is paused, event period will not be updated until the next time it's resumed or reprogrammed. And there is also no need to call perf_event_period twice for a non-running counter, considering the perf_event for a running counter is never paused. Based on this implementation, for the following common usage of sampling 4 events using perf on a 4u8g guest: echo 0 > /proc/sys/kernel/watchdog echo 25 > /proc/sys/kernel/perf_cpu_time_max_percent echo 10000 > /proc/sys/kernel/perf_event_max_sample_rate echo 0 > /proc/sys/kernel/perf_cpu_time_max_percent for i in `seq 1 1 10` do taskset -c 0 perf record \ -e cpu-cycles -e instructions -e branch-instructions -e cache-misses \ /root/br_instr a done the average latency of the guest NMI handler is reduced from 37646.7 ns to 32929.3 ns (~1.14x speed up) on the Intel ICX server. Also, in addition to collecting more samples, no loss of sampling accuracy was observed compared to before the optimization. Signed-off-by: Like Xu <likexu@tencent.com> Message-Id: <20210728120705.6855-1-likexu@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Peter Zijlstra <peterz@infradead.org>
535 lines
14 KiB
C
535 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Kernel-based Virtual Machine -- Performance Monitoring Unit support
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*
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* Copyright 2015 Red Hat, Inc. and/or its affiliates.
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*
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* Authors:
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* Avi Kivity <avi@redhat.com>
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* Gleb Natapov <gleb@redhat.com>
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* Wei Huang <wei@redhat.com>
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*/
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <asm/perf_event.h>
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#include "x86.h"
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#include "cpuid.h"
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#include "lapic.h"
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#include "pmu.h"
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/* This is enough to filter the vast majority of currently defined events. */
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#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
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/* NOTE:
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* - Each perf counter is defined as "struct kvm_pmc";
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* - There are two types of perf counters: general purpose (gp) and fixed.
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* gp counters are stored in gp_counters[] and fixed counters are stored
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* in fixed_counters[] respectively. Both of them are part of "struct
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* kvm_pmu";
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* - pmu.c understands the difference between gp counters and fixed counters.
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* However AMD doesn't support fixed-counters;
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* - There are three types of index to access perf counters (PMC):
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* 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
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* has MSR_K7_PERFCTRn.
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* 2. MSR Index (named idx): This normally is used by RDPMC instruction.
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* For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
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* C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
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* that it also supports fixed counters. idx can be used to as index to
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* gp and fixed counters.
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* 3. Global PMC Index (named pmc): pmc is an index specific to PMU
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* code. Each pmc, stored in kvm_pmc.idx field, is unique across
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* all perf counters (both gp and fixed). The mapping relationship
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* between pmc and perf counters is as the following:
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* * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
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* [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
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* * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters
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*/
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static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
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{
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struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
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struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
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kvm_pmu_deliver_pmi(vcpu);
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}
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static void kvm_perf_overflow(struct perf_event *perf_event,
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struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct kvm_pmc *pmc = perf_event->overflow_handler_context;
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (!test_and_set_bit(pmc->idx, pmu->reprogram_pmi)) {
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__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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}
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}
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static void kvm_perf_overflow_intr(struct perf_event *perf_event,
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struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct kvm_pmc *pmc = perf_event->overflow_handler_context;
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (!test_and_set_bit(pmc->idx, pmu->reprogram_pmi)) {
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__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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/*
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* Inject PMI. If vcpu was in a guest mode during NMI PMI
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* can be ejected on a guest mode re-entry. Otherwise we can't
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* be sure that vcpu wasn't executing hlt instruction at the
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* time of vmexit and is not going to re-enter guest mode until
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* woken up. So we should wake it, but this is impossible from
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* NMI context. Do it from irq work instead.
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*/
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if (!kvm_is_in_guest())
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irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
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else
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kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
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}
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}
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static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
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unsigned config, bool exclude_user,
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bool exclude_kernel, bool intr,
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bool in_tx, bool in_tx_cp)
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{
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struct perf_event *event;
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struct perf_event_attr attr = {
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.type = type,
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.size = sizeof(attr),
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.pinned = true,
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.exclude_idle = true,
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.exclude_host = 1,
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.exclude_user = exclude_user,
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.exclude_kernel = exclude_kernel,
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.config = config,
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};
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attr.sample_period = get_sample_period(pmc, pmc->counter);
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if (in_tx)
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attr.config |= HSW_IN_TX;
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if (in_tx_cp) {
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/*
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* HSW_IN_TX_CHECKPOINTED is not supported with nonzero
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* period. Just clear the sample period so at least
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* allocating the counter doesn't fail.
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*/
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attr.sample_period = 0;
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attr.config |= HSW_IN_TX_CHECKPOINTED;
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}
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event = perf_event_create_kernel_counter(&attr, -1, current,
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intr ? kvm_perf_overflow_intr :
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kvm_perf_overflow, pmc);
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if (IS_ERR(event)) {
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pr_debug_ratelimited("kvm_pmu: event creation failed %ld for pmc->idx = %d\n",
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PTR_ERR(event), pmc->idx);
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return;
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}
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pmc->perf_event = event;
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pmc_to_pmu(pmc)->event_count++;
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clear_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
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pmc->is_paused = false;
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}
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static void pmc_pause_counter(struct kvm_pmc *pmc)
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{
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u64 counter = pmc->counter;
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if (!pmc->perf_event || pmc->is_paused)
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return;
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/* update counter, reset event value to avoid redundant accumulation */
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counter += perf_event_pause(pmc->perf_event, true);
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pmc->counter = counter & pmc_bitmask(pmc);
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pmc->is_paused = true;
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}
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static bool pmc_resume_counter(struct kvm_pmc *pmc)
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{
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if (!pmc->perf_event)
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return false;
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/* recalibrate sample period and check if it's accepted by perf core */
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if (perf_event_period(pmc->perf_event,
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get_sample_period(pmc, pmc->counter)))
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return false;
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/* reuse perf_event to serve as pmc_reprogram_counter() does*/
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perf_event_enable(pmc->perf_event);
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pmc->is_paused = false;
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clear_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->reprogram_pmi);
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return true;
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}
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void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
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{
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unsigned config, type = PERF_TYPE_RAW;
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u8 event_select, unit_mask;
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struct kvm *kvm = pmc->vcpu->kvm;
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struct kvm_pmu_event_filter *filter;
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int i;
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bool allow_event = true;
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if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
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printk_once("kvm pmu: pin control bit is ignored\n");
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pmc->eventsel = eventsel;
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pmc_pause_counter(pmc);
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if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
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return;
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filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
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if (filter) {
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for (i = 0; i < filter->nevents; i++)
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if (filter->events[i] ==
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(eventsel & AMD64_RAW_EVENT_MASK_NB))
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break;
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if (filter->action == KVM_PMU_EVENT_ALLOW &&
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i == filter->nevents)
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allow_event = false;
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if (filter->action == KVM_PMU_EVENT_DENY &&
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i < filter->nevents)
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allow_event = false;
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}
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if (!allow_event)
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return;
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event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
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unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
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if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
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ARCH_PERFMON_EVENTSEL_INV |
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ARCH_PERFMON_EVENTSEL_CMASK |
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HSW_IN_TX |
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HSW_IN_TX_CHECKPOINTED))) {
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config = kvm_x86_ops.pmu_ops->find_arch_event(pmc_to_pmu(pmc),
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event_select,
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unit_mask);
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if (config != PERF_COUNT_HW_MAX)
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type = PERF_TYPE_HARDWARE;
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}
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if (type == PERF_TYPE_RAW)
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config = eventsel & X86_RAW_EVENT_MASK;
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if (pmc->current_config == eventsel && pmc_resume_counter(pmc))
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return;
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pmc_release_perf_event(pmc);
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pmc->current_config = eventsel;
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pmc_reprogram_counter(pmc, type, config,
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!(eventsel & ARCH_PERFMON_EVENTSEL_USR),
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!(eventsel & ARCH_PERFMON_EVENTSEL_OS),
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eventsel & ARCH_PERFMON_EVENTSEL_INT,
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(eventsel & HSW_IN_TX),
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(eventsel & HSW_IN_TX_CHECKPOINTED));
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}
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EXPORT_SYMBOL_GPL(reprogram_gp_counter);
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void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
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{
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unsigned en_field = ctrl & 0x3;
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bool pmi = ctrl & 0x8;
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struct kvm_pmu_event_filter *filter;
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struct kvm *kvm = pmc->vcpu->kvm;
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pmc_pause_counter(pmc);
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if (!en_field || !pmc_is_enabled(pmc))
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return;
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filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
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if (filter) {
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if (filter->action == KVM_PMU_EVENT_DENY &&
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test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
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return;
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if (filter->action == KVM_PMU_EVENT_ALLOW &&
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!test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
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return;
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}
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if (pmc->current_config == (u64)ctrl && pmc_resume_counter(pmc))
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return;
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pmc_release_perf_event(pmc);
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pmc->current_config = (u64)ctrl;
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pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
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kvm_x86_ops.pmu_ops->find_fixed_event(idx),
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!(en_field & 0x2), /* exclude user */
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!(en_field & 0x1), /* exclude kernel */
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pmi, false, false);
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}
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EXPORT_SYMBOL_GPL(reprogram_fixed_counter);
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void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
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{
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struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, pmc_idx);
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if (!pmc)
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return;
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if (pmc_is_gp(pmc))
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reprogram_gp_counter(pmc, pmc->eventsel);
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else {
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int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
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u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
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reprogram_fixed_counter(pmc, ctrl, idx);
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}
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}
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EXPORT_SYMBOL_GPL(reprogram_counter);
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void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int bit;
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for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) {
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struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, bit);
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if (unlikely(!pmc || !pmc->perf_event)) {
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clear_bit(bit, pmu->reprogram_pmi);
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continue;
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}
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reprogram_counter(pmu, bit);
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}
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/*
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* Unused perf_events are only released if the corresponding MSRs
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* weren't accessed during the last vCPU time slice. kvm_arch_sched_in
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* triggers KVM_REQ_PMU if cleanup is needed.
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*/
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if (unlikely(pmu->need_cleanup))
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kvm_pmu_cleanup(vcpu);
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}
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/* check if idx is a valid index to access PMU */
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int kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
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{
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return kvm_x86_ops.pmu_ops->is_valid_rdpmc_ecx(vcpu, idx);
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}
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bool is_vmware_backdoor_pmc(u32 pmc_idx)
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{
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switch (pmc_idx) {
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case VMWARE_BACKDOOR_PMC_HOST_TSC:
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case VMWARE_BACKDOOR_PMC_REAL_TIME:
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case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
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return true;
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}
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return false;
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}
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static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
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{
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u64 ctr_val;
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switch (idx) {
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case VMWARE_BACKDOOR_PMC_HOST_TSC:
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ctr_val = rdtsc();
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break;
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case VMWARE_BACKDOOR_PMC_REAL_TIME:
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ctr_val = ktime_get_boottime_ns();
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break;
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case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
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ctr_val = ktime_get_boottime_ns() +
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vcpu->kvm->arch.kvmclock_offset;
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break;
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default:
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return 1;
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}
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*data = ctr_val;
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return 0;
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}
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int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
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{
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bool fast_mode = idx & (1u << 31);
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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u64 mask = fast_mode ? ~0u : ~0ull;
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if (!pmu->version)
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return 1;
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if (is_vmware_backdoor_pmc(idx))
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return kvm_pmu_rdpmc_vmware(vcpu, idx, data);
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pmc = kvm_x86_ops.pmu_ops->rdpmc_ecx_to_pmc(vcpu, idx, &mask);
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if (!pmc)
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return 1;
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if (!(kvm_read_cr4(vcpu) & X86_CR4_PCE) &&
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(static_call(kvm_x86_get_cpl)(vcpu) != 0) &&
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(kvm_read_cr0(vcpu) & X86_CR0_PE))
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return 1;
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*data = pmc_read_counter(pmc) & mask;
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return 0;
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}
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void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
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{
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if (lapic_in_kernel(vcpu)) {
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if (kvm_x86_ops.pmu_ops->deliver_pmi)
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kvm_x86_ops.pmu_ops->deliver_pmi(vcpu);
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kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
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}
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}
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bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
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{
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return kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr) ||
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kvm_x86_ops.pmu_ops->is_valid_msr(vcpu, msr);
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}
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static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr);
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if (pmc)
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__set_bit(pmc->idx, pmu->pmc_in_use);
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}
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int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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return kvm_x86_ops.pmu_ops->get_msr(vcpu, msr_info);
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}
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int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
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return kvm_x86_ops.pmu_ops->set_msr(vcpu, msr_info);
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}
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/* refresh PMU settings. This function generally is called when underlying
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* settings are changed (such as changes of PMU CPUID by guest VMs), which
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* should rarely happen.
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*/
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void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
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{
|
|
kvm_x86_ops.pmu_ops->refresh(vcpu);
|
|
}
|
|
|
|
void kvm_pmu_reset(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
|
|
irq_work_sync(&pmu->irq_work);
|
|
kvm_x86_ops.pmu_ops->reset(vcpu);
|
|
}
|
|
|
|
void kvm_pmu_init(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
|
|
memset(pmu, 0, sizeof(*pmu));
|
|
kvm_x86_ops.pmu_ops->init(vcpu);
|
|
init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
|
|
pmu->event_count = 0;
|
|
pmu->need_cleanup = false;
|
|
kvm_pmu_refresh(vcpu);
|
|
}
|
|
|
|
static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
|
|
{
|
|
struct kvm_pmu *pmu = pmc_to_pmu(pmc);
|
|
|
|
if (pmc_is_fixed(pmc))
|
|
return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
|
|
pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
|
|
|
|
return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
|
|
}
|
|
|
|
/* Release perf_events for vPMCs that have been unused for a full time slice. */
|
|
void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc = NULL;
|
|
DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX);
|
|
int i;
|
|
|
|
pmu->need_cleanup = false;
|
|
|
|
bitmap_andnot(bitmask, pmu->all_valid_pmc_idx,
|
|
pmu->pmc_in_use, X86_PMC_IDX_MAX);
|
|
|
|
for_each_set_bit(i, bitmask, X86_PMC_IDX_MAX) {
|
|
pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, i);
|
|
|
|
if (pmc && pmc->perf_event && !pmc_speculative_in_use(pmc))
|
|
pmc_stop_counter(pmc);
|
|
}
|
|
|
|
if (kvm_x86_ops.pmu_ops->cleanup)
|
|
kvm_x86_ops.pmu_ops->cleanup(vcpu);
|
|
|
|
bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);
|
|
}
|
|
|
|
void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
|
|
{
|
|
kvm_pmu_reset(vcpu);
|
|
}
|
|
|
|
int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp)
|
|
{
|
|
struct kvm_pmu_event_filter tmp, *filter;
|
|
size_t size;
|
|
int r;
|
|
|
|
if (copy_from_user(&tmp, argp, sizeof(tmp)))
|
|
return -EFAULT;
|
|
|
|
if (tmp.action != KVM_PMU_EVENT_ALLOW &&
|
|
tmp.action != KVM_PMU_EVENT_DENY)
|
|
return -EINVAL;
|
|
|
|
if (tmp.flags != 0)
|
|
return -EINVAL;
|
|
|
|
if (tmp.nevents > KVM_PMU_EVENT_FILTER_MAX_EVENTS)
|
|
return -E2BIG;
|
|
|
|
size = struct_size(filter, events, tmp.nevents);
|
|
filter = kmalloc(size, GFP_KERNEL_ACCOUNT);
|
|
if (!filter)
|
|
return -ENOMEM;
|
|
|
|
r = -EFAULT;
|
|
if (copy_from_user(filter, argp, size))
|
|
goto cleanup;
|
|
|
|
/* Ensure nevents can't be changed between the user copies. */
|
|
*filter = tmp;
|
|
|
|
mutex_lock(&kvm->lock);
|
|
filter = rcu_replace_pointer(kvm->arch.pmu_event_filter, filter,
|
|
mutex_is_locked(&kvm->lock));
|
|
mutex_unlock(&kvm->lock);
|
|
|
|
synchronize_srcu_expedited(&kvm->srcu);
|
|
r = 0;
|
|
cleanup:
|
|
kfree(filter);
|
|
return r;
|
|
}
|