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bb8958d5dc
On SiFive Unmatched, I recently fell onto the following BUG when booting:
[ 0.000000] ftrace: allocating 36610 entries in 144 pages
[ 0.000000] Oops - illegal instruction [#1]
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.13.1+ #5
[ 0.000000] Hardware name: SiFive HiFive Unmatched A00 (DT)
[ 0.000000] epc : riscv_cpuid_to_hartid_mask+0x6/0xae
[ 0.000000] ra : __sbi_rfence_v02+0xc8/0x10a
[ 0.000000] epc : ffffffff80007240 ra : ffffffff80009964 sp : ffffffff81803e10
[ 0.000000] gp : ffffffff81a1ea70 tp : ffffffff8180f500 t0 : ffffffe07fe30000
[ 0.000000] t1 : 0000000000000004 t2 : 0000000000000000 s0 : ffffffff81803e60
[ 0.000000] s1 : 0000000000000000 a0 : ffffffff81a22238 a1 : ffffffff81803e10
[ 0.000000] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
[ 0.000000] a5 : 0000000000000000 a6 : ffffffff8000989c a7 : 0000000052464e43
[ 0.000000] s2 : ffffffff81a220c8 s3 : 0000000000000000 s4 : 0000000000000000
[ 0.000000] s5 : 0000000000000000 s6 : 0000000200000100 s7 : 0000000000000001
[ 0.000000] s8 : ffffffe07fe04040 s9 : ffffffff81a22c80 s10: 0000000000001000
[ 0.000000] s11: 0000000000000004 t3 : 0000000000000001 t4 : 0000000000000008
[ 0.000000] t5 : ffffffcf04000808 t6 : ffffffe3ffddf188
[ 0.000000] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000002
[ 0.000000] [<ffffffff80007240>] riscv_cpuid_to_hartid_mask+0x6/0xae
[ 0.000000] [<ffffffff80009474>] sbi_remote_fence_i+0x1e/0x26
[ 0.000000] [<ffffffff8000b8f4>] flush_icache_all+0x12/0x1a
[ 0.000000] [<ffffffff8000666c>] patch_text_nosync+0x26/0x32
[ 0.000000] [<ffffffff8000884e>] ftrace_init_nop+0x52/0x8c
[ 0.000000] [<ffffffff800f051e>] ftrace_process_locs.isra.0+0x29c/0x360
[ 0.000000] [<ffffffff80a0e3c6>] ftrace_init+0x80/0x130
[ 0.000000] [<ffffffff80a00f8c>] start_kernel+0x5c4/0x8f6
[ 0.000000] ---[ end trace f67eb9af4d8d492b ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
While ftrace is looping over a list of addresses to patch, it always failed
when patching the same function: riscv_cpuid_to_hartid_mask. Looking at the
backtrace, the illegal instruction is encountered in this same function.
However, patch_text_nosync, after patching the instructions, calls
flush_icache_range. But looking at what happens in this function:
flush_icache_range -> flush_icache_all
-> sbi_remote_fence_i
-> __sbi_rfence_v02
-> riscv_cpuid_to_hartid_mask
The icache and dcache of the current cpu are never synchronized between the
patching of riscv_cpuid_to_hartid_mask and calling this same function.
So fix this by flushing the current cpu's icache before asking for the other
cpus to do the same.
Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
Fixes: fab957c11e ("RISC-V: Atomic and Locking Code")
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 SiFive
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*/
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#include <asm/cacheflush.h>
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#ifdef CONFIG_SMP
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#include <asm/sbi.h>
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static void ipi_remote_fence_i(void *info)
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{
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return local_flush_icache_all();
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}
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void flush_icache_all(void)
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{
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local_flush_icache_all();
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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sbi_remote_fence_i(NULL);
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else
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on_each_cpu(ipi_remote_fence_i, NULL, 1);
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}
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EXPORT_SYMBOL(flush_icache_all);
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/*
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* Performs an icache flush for the given MM context. RISC-V has no direct
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* mechanism for instruction cache shoot downs, so instead we send an IPI that
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* informs the remote harts they need to flush their local instruction caches.
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* To avoid pathologically slow behavior in a common case (a bunch of
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* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
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* IPIs for harts that are not currently executing a MM context and instead
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* schedule a deferred local instruction cache flush to be performed before
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* execution resumes on each hart.
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*/
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void flush_icache_mm(struct mm_struct *mm, bool local)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_flush_icache_all();
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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local |= cpumask_empty(&others);
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if (mm == current->active_mm && local) {
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/*
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* It's assumed that at least one strongly ordered operation is
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* performed on this hart between setting a hart's cpumask bit
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* and scheduling this MM context on that hart. Sending an SBI
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* remote message will do this, but in the case where no
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* messages are sent we still need to order this hart's writes
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* with flush_icache_deferred().
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*/
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smp_mb();
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} else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
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cpumask_t hartid_mask;
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riscv_cpuid_to_hartid_mask(&others, &hartid_mask);
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sbi_remote_fence_i(cpumask_bits(&hartid_mask));
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} else {
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on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
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}
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preempt_enable();
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}
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_MMU
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void flush_icache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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flush_icache_all();
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}
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#endif /* CONFIG_MMU */
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