mirror of
https://github.com/torvalds/linux.git
synced 2024-12-12 22:23:55 +00:00
7d839b4b9e
Adds a new driver to support the SMMUv3 PMU and add it into the
perf events framework.
Each SMMU node may have multiple PMUs associated with it, each of
which may support different events.
SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
<phys_addr_page> is the physical page address of the SMMU PMCG
wrapped to 4K boundary. For example, the PMCG at 0xff88840000 is
named smmuv3_pmcg_ff88840
Filtering by stream id is done by specifying filtering parameters
with the event. options are:
filter_enable - 0 = no filtering, 1 = filtering enabled
filter_span - 0 = exact match, 1 = pattern match
filter_stream_id - pattern to filter against
Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
filter_span=1,filter_stream_id=0x42/ -a netperf
Applies filter pattern 0x42 to transaction events, which means events
matching stream ids 0x42 & 0x43 are counted as only upper StreamID
bits are required to match the given filter. Further filtering
information is available in the SMMU documentation.
SMMU events are not attributable to a CPU, so task mode and sampling
are not supported.
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
[will: fold in review feedback from Robin]
[will: rewrite Kconfig text and allow building as a module]
Signed-off-by: Will Deacon <will.deacon@arm.com>
124 lines
3.6 KiB
Plaintext
124 lines
3.6 KiB
Plaintext
#
|
|
# Performance Monitor Drivers
|
|
#
|
|
|
|
menu "Performance monitor support"
|
|
depends on PERF_EVENTS
|
|
|
|
config ARM_CCI_PMU
|
|
tristate "ARM CCI PMU driver"
|
|
depends on (ARM && CPU_V7) || ARM64
|
|
select ARM_CCI
|
|
help
|
|
Support for PMU events monitoring on the ARM CCI (Cache Coherent
|
|
Interconnect) family of products.
|
|
|
|
If compiled as a module, it will be called arm-cci.
|
|
|
|
config ARM_CCI400_PMU
|
|
bool "support CCI-400"
|
|
default y
|
|
depends on ARM_CCI_PMU
|
|
select ARM_CCI400_COMMON
|
|
help
|
|
CCI-400 provides 4 independent event counters counting events related
|
|
to the connected slave/master interfaces, plus a cycle counter.
|
|
|
|
config ARM_CCI5xx_PMU
|
|
bool "support CCI-500/CCI-550"
|
|
default y
|
|
depends on ARM_CCI_PMU
|
|
help
|
|
CCI-500/CCI-550 both provide 8 independent event counters, which can
|
|
count events pertaining to the slave/master interfaces as well as the
|
|
internal events to the CCI.
|
|
|
|
config ARM_CCN
|
|
tristate "ARM CCN driver support"
|
|
depends on ARM || ARM64
|
|
help
|
|
PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
|
|
interconnect.
|
|
|
|
config ARM_PMU
|
|
depends on ARM || ARM64
|
|
bool "ARM PMU framework"
|
|
default y
|
|
help
|
|
Say y if you want to use CPU performance monitors on ARM-based
|
|
systems.
|
|
|
|
config ARM_PMU_ACPI
|
|
depends on ARM_PMU && ACPI
|
|
def_bool y
|
|
|
|
config ARM_SMMU_V3_PMU
|
|
tristate "ARM SMMUv3 Performance Monitors Extension"
|
|
depends on ARM64 && ACPI && ARM_SMMU_V3
|
|
help
|
|
Provides support for the ARM SMMUv3 Performance Monitor Counter
|
|
Groups (PMCG), which provide monitoring of transactions passing
|
|
through the SMMU and allow the resulting information to be filtered
|
|
based on the Stream ID of the corresponding master.
|
|
|
|
config ARM_DSU_PMU
|
|
tristate "ARM DynamIQ Shared Unit (DSU) PMU"
|
|
depends on ARM64
|
|
help
|
|
Provides support for performance monitor unit in ARM DynamIQ Shared
|
|
Unit (DSU). The DSU integrates one or more cores with an L3 memory
|
|
system, control logic. The PMU allows counting various events related
|
|
to DSU.
|
|
|
|
config HISI_PMU
|
|
bool "HiSilicon SoC PMU"
|
|
depends on ARM64 && ACPI
|
|
help
|
|
Support for HiSilicon SoC uncore performance monitoring
|
|
unit (PMU), such as: L3C, HHA and DDRC.
|
|
|
|
config QCOM_L2_PMU
|
|
bool "Qualcomm Technologies L2-cache PMU"
|
|
depends on ARCH_QCOM && ARM64 && ACPI
|
|
help
|
|
Provides support for the L2 cache performance monitor unit (PMU)
|
|
in Qualcomm Technologies processors.
|
|
Adds the L2 cache PMU into the perf events subsystem for
|
|
monitoring L2 cache events.
|
|
|
|
config QCOM_L3_PMU
|
|
bool "Qualcomm Technologies L3-cache PMU"
|
|
depends on ARCH_QCOM && ARM64 && ACPI
|
|
select QCOM_IRQ_COMBINER
|
|
help
|
|
Provides support for the L3 cache performance monitor unit (PMU)
|
|
in Qualcomm Technologies processors.
|
|
Adds the L3 cache PMU into the perf events subsystem for
|
|
monitoring L3 cache events.
|
|
|
|
config THUNDERX2_PMU
|
|
tristate "Cavium ThunderX2 SoC PMU UNCORE"
|
|
depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
|
|
default m
|
|
help
|
|
Provides support for ThunderX2 UNCORE events.
|
|
The SoC has PMU support in its L3 cache controller (L3C) and
|
|
in the DDR4 Memory Controller (DMC).
|
|
|
|
config XGENE_PMU
|
|
depends on ARCH_XGENE
|
|
bool "APM X-Gene SoC PMU"
|
|
default n
|
|
help
|
|
Say y if you want to use APM X-Gene SoC performance monitors.
|
|
|
|
config ARM_SPE_PMU
|
|
tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
|
|
depends on ARM64
|
|
help
|
|
Enable perf support for the ARMv8.2 Statistical Profiling
|
|
Extension, which provides periodic sampling of operations in
|
|
the CPU pipeline and reports this via the perf AUX interface.
|
|
|
|
endmenu
|