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135 lines
3.7 KiB
C
135 lines
3.7 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_vm.h"
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void
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nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
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struct nouveau_gpuobj *pgt[2])
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{
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u32 pde[2] = { 0, 0 };
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if (pgt[0])
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pde[1] = 0x00000001 | (pgt[0]->vinst >> 8);
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if (pgt[1])
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pde[0] = 0x00000001 | (pgt[1]->vinst >> 8);
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nv_wo32(pgd, (index * 8) + 0, pde[0]);
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nv_wo32(pgd, (index * 8) + 4, pde[1]);
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}
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static inline u64
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nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
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{
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phys >>= 8;
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phys |= 0x00000001; /* present */
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if (vma->access & NV_MEM_ACCESS_SYS)
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phys |= 0x00000002;
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phys |= ((u64)target << 32);
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phys |= ((u64)memtype << 36);
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return phys;
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}
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void
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nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
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{
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u32 next = 1 << (vma->node->type - 8);
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phys = nvc0_vm_addr(vma, phys, mem->memtype, 0);
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pte <<= 3;
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while (cnt--) {
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nv_wo32(pgt, pte + 0, lower_32_bits(phys));
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nv_wo32(pgt, pte + 4, upper_32_bits(phys));
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phys += next;
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pte += 8;
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}
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}
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void
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nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
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{
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pte <<= 3;
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while (cnt--) {
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u64 phys = nvc0_vm_addr(vma, *list++, mem->memtype, 5);
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nv_wo32(pgt, pte + 0, lower_32_bits(phys));
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nv_wo32(pgt, pte + 4, upper_32_bits(phys));
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pte += 8;
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}
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}
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void
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nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
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{
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pte <<= 3;
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while (cnt--) {
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nv_wo32(pgt, pte + 0, 0x00000000);
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nv_wo32(pgt, pte + 4, 0x00000000);
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pte += 8;
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}
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}
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void
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nvc0_vm_flush(struct nouveau_vm *vm)
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{
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struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct drm_device *dev = vm->dev;
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struct nouveau_vm_pgd *vpgd;
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unsigned long flags;
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u32 engine;
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engine = 1;
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if (vm == dev_priv->bar1_vm || vm == dev_priv->bar3_vm)
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engine |= 4;
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pinstmem->flush(vm->dev);
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spin_lock_irqsave(&dev_priv->vm_lock, flags);
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list_for_each_entry(vpgd, &vm->pgd_list, head) {
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/* looks like maybe a "free flush slots" counter, the
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* faster you write to 0x100cbc to more it decreases
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*/
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if (!nv_wait_ne(dev, 0x100c80, 0x00ff0000, 0x00000000)) {
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NV_ERROR(dev, "vm timeout 0: 0x%08x %d\n",
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nv_rd32(dev, 0x100c80), engine);
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}
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nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
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nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
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/* wait for flush to be queued? */
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if (!nv_wait(dev, 0x100c80, 0x00008000, 0x00008000)) {
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NV_ERROR(dev, "vm timeout 1: 0x%08x %d\n",
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nv_rd32(dev, 0x100c80), engine);
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}
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}
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spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
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}
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