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If we power off the SoC logic rail in S3, we can find that the Type-C PHY can't initialize correctly after system resume. We need to toggle the USB3-OTG reset before trying to initialize the PHY, or else it times out. phy phy-ff800000.phy.9: phy poweron failed --> -110 dwc3 fe900000.dwc3: failed to initialize core dwc3: probe of fe900000.dwc3 failed with error -110 Note that the RK3399 TRM suggests that we should keep the whole usb3 controller in reset for the duration of the Type-C PHY initialization. However, it's hard to assert the reset in the current framework of reset. We're still skeptical about that, and we haven't yet found a case where this seems to have mattered. This approach is much easier, it simply holds the USB3-OTG reset while device is supended. The dwc3 core is going to reinitialize the controller at suspend/resume anyway (including a "soft reset"), so it should be safe to do this. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
266 lines
6.0 KiB
C
266 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/**
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* dwc3-of-simple.c - OF glue layer for simple integrations
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*
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* Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
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*
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* Author: Felipe Balbi <balbi@ti.com>
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*
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* This is a combination of the old dwc3-qcom.c by Ivan T. Ivanov
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* <iivanov@mm-sol.com> and the original patch adding support for Xilinx' SoC
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* by Subbaraya Sundeep Bhatta <subbaraya.sundeep.bhatta@xilinx.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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struct dwc3_of_simple {
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struct device *dev;
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struct clk **clks;
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int num_clocks;
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struct reset_control *resets;
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bool pulse_resets;
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bool need_reset;
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};
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static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)
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{
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struct device *dev = simple->dev;
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struct device_node *np = dev->of_node;
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int i;
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simple->num_clocks = count;
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if (!count)
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return 0;
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simple->clks = devm_kcalloc(dev, simple->num_clocks,
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sizeof(struct clk *), GFP_KERNEL);
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if (!simple->clks)
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return -ENOMEM;
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for (i = 0; i < simple->num_clocks; i++) {
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struct clk *clk;
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int ret;
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clk = of_clk_get(np, i);
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if (IS_ERR(clk)) {
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while (--i >= 0) {
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clk_disable_unprepare(simple->clks[i]);
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clk_put(simple->clks[i]);
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}
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret < 0) {
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while (--i >= 0) {
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clk_disable_unprepare(simple->clks[i]);
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clk_put(simple->clks[i]);
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}
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clk_put(clk);
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return ret;
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}
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simple->clks[i] = clk;
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}
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return 0;
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}
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static int dwc3_of_simple_probe(struct platform_device *pdev)
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{
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struct dwc3_of_simple *simple;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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int ret;
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int i;
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bool shared_resets = false;
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simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
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if (!simple)
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return -ENOMEM;
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platform_set_drvdata(pdev, simple);
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simple->dev = dev;
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/*
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* Some controllers need to toggle the usb3-otg reset before trying to
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* initialize the PHY, otherwise the PHY times out.
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*/
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if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
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simple->need_reset = true;
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if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") ||
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of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) {
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shared_resets = true;
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simple->pulse_resets = true;
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}
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simple->resets = of_reset_control_array_get(np, shared_resets, true);
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if (IS_ERR(simple->resets)) {
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ret = PTR_ERR(simple->resets);
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dev_err(dev, "failed to get device resets, err=%d\n", ret);
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return ret;
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}
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if (simple->pulse_resets) {
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ret = reset_control_reset(simple->resets);
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if (ret)
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goto err_resetc_put;
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} else {
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ret = reset_control_deassert(simple->resets);
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if (ret)
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goto err_resetc_put;
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}
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ret = dwc3_of_simple_clk_init(simple, of_count_phandle_with_args(np,
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"clocks", "#clock-cells"));
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if (ret)
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goto err_resetc_assert;
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ret = of_platform_populate(np, NULL, NULL, dev);
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if (ret) {
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for (i = 0; i < simple->num_clocks; i++) {
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clk_disable_unprepare(simple->clks[i]);
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clk_put(simple->clks[i]);
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}
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goto err_resetc_assert;
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}
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
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return 0;
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err_resetc_assert:
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if (!simple->pulse_resets)
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reset_control_assert(simple->resets);
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err_resetc_put:
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reset_control_put(simple->resets);
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return ret;
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}
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static int dwc3_of_simple_remove(struct platform_device *pdev)
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{
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struct dwc3_of_simple *simple = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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int i;
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of_platform_depopulate(dev);
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for (i = 0; i < simple->num_clocks; i++) {
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clk_disable_unprepare(simple->clks[i]);
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clk_put(simple->clks[i]);
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}
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simple->num_clocks = 0;
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if (!simple->pulse_resets)
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reset_control_assert(simple->resets);
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reset_control_put(simple->resets);
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pm_runtime_disable(dev);
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pm_runtime_put_noidle(dev);
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pm_runtime_set_suspended(dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int dwc3_of_simple_runtime_suspend(struct device *dev)
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{
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struct dwc3_of_simple *simple = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < simple->num_clocks; i++)
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clk_disable(simple->clks[i]);
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return 0;
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}
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static int dwc3_of_simple_runtime_resume(struct device *dev)
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{
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struct dwc3_of_simple *simple = dev_get_drvdata(dev);
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int ret;
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int i;
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for (i = 0; i < simple->num_clocks; i++) {
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ret = clk_enable(simple->clks[i]);
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if (ret < 0) {
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while (--i >= 0)
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clk_disable(simple->clks[i]);
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return ret;
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}
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}
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return 0;
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}
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static int dwc3_of_simple_suspend(struct device *dev)
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{
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struct dwc3_of_simple *simple = dev_get_drvdata(dev);
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if (simple->need_reset)
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reset_control_assert(simple->resets);
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return 0;
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}
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static int dwc3_of_simple_resume(struct device *dev)
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{
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struct dwc3_of_simple *simple = dev_get_drvdata(dev);
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if (simple->need_reset)
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reset_control_deassert(simple->resets);
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return 0;
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}
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#endif
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static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(dwc3_of_simple_suspend, dwc3_of_simple_resume)
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SET_RUNTIME_PM_OPS(dwc3_of_simple_runtime_suspend,
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dwc3_of_simple_runtime_resume, NULL)
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};
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static const struct of_device_id of_dwc3_simple_match[] = {
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{ .compatible = "rockchip,rk3399-dwc3" },
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{ .compatible = "xlnx,zynqmp-dwc3" },
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{ .compatible = "cavium,octeon-7130-usb-uctl" },
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{ .compatible = "sprd,sc9860-dwc3" },
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{ .compatible = "amlogic,meson-axg-dwc3" },
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{ .compatible = "amlogic,meson-gxl-dwc3" },
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{ .compatible = "allwinner,sun50i-h6-dwc3" },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
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static struct platform_driver dwc3_of_simple_driver = {
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.probe = dwc3_of_simple_probe,
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.remove = dwc3_of_simple_remove,
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.driver = {
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.name = "dwc3-of-simple",
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.of_match_table = of_dwc3_simple_match,
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.pm = &dwc3_of_simple_dev_pm_ops,
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},
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};
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module_platform_driver(dwc3_of_simple_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("DesignWare USB3 OF Simple Glue Layer");
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MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
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