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dfd437a257
- arm64 support for syscall emulation via PTRACE_SYSEMU{,_SINGLESTEP} - Wire up VM_FLUSH_RESET_PERMS for arm64, allowing the core code to manage the permissions of executable vmalloc regions more strictly - Slight performance improvement by keeping softirqs enabled while touching the FPSIMD/SVE state (kernel_neon_begin/end) - Expose a couple of ARMv8.5 features to user (HWCAP): CondM (new XAFLAG and AXFLAG instructions for floating point comparison flags manipulation) and FRINT (rounding floating point numbers to integers) - Re-instate ARM64_PSEUDO_NMI support which was previously marked as BROKEN due to some bugs (now fixed) - Improve parking of stopped CPUs and implement an arm64-specific panic_smp_self_stop() to avoid warning on not being able to stop secondary CPUs during panic - perf: enable the ARM Statistical Profiling Extensions (SPE) on ACPI platforms - perf: DDR performance monitor support for iMX8QXP - cache_line_size() can now be set from DT or ACPI/PPTT if provided to cope with a system cache info not exposed via the CPUID registers - Avoid warning on hardware cache line size greater than ARCH_DMA_MINALIGN if the system is fully coherent - arm64 do_page_fault() and hugetlb cleanups - Refactor set_pte_at() to avoid redundant READ_ONCE(*ptep) - Ignore ACPI 5.1 FADTs reported as 5.0 (infer from the 'arm_boot_flags' introduced in 5.1) - CONFIG_RANDOMIZE_BASE now enabled in defconfig - Allow the selection of ARM64_MODULE_PLTS, currently only done via RANDOMIZE_BASE (and an erratum workaround), allowing modules to spill over into the vmalloc area - Make ZONE_DMA32 configurable -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAl0eHqcACgkQa9axLQDI XvFyNA/+L+bnkz8m3ncydlqqfXomQn4eJJVQ8Uksb0knJz+1+3CUxxbO4ry4jXZN fMkbggYrDPRKpDbsUl0lsRipj7jW9bqan+N37c3SWqCkgb6HqDaHViwxdx6Ec/Uk gHudozDSPh/8c7hxGcSyt/CFyuW6b+8eYIQU5rtIgz8aVY2BypBvS/7YtYCbIkx0 w4CFleRTK1zXD5mJQhrc6jyDx659sVkrAvdhf6YIymOY8nBTv40vwdNo3beJMYp8 Po/+0Ixu+VkHUNtmYYZQgP/AGH96xiTcRnUqd172JdtRPpCLqnLqwFokXeVIlUKT KZFMDPzK+756Ayn4z4huEePPAOGlHbJje8JVNnFyreKhVVcCotW7YPY/oJR10bnc eo7yD+DxABTn+93G2yP436bNVa8qO1UqjOBfInWBtnNFJfANIkZweij/MQ6MjaTA o7KtviHnZFClefMPoiI7HDzwL8XSmsBDbeQ04s2Wxku1Y2xUHLx4iLmadwLQ1ZPb lZMTZP3N/T1554MoURVA1afCjAwiqU3bt1xDUGjbBVjLfSPBAn/25IacsG9Li9AF 7Rp1M9VhrfLftjFFkB2HwpbhRASOxaOSx+EI3kzEfCtM2O9I1WHgP3rvCdc3l0HU tbK0/IggQicNgz7GSZ8xDlWPwwSadXYGLys+xlMZEYd3pDIOiFc= =0TDT -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - arm64 support for syscall emulation via PTRACE_SYSEMU{,_SINGLESTEP} - Wire up VM_FLUSH_RESET_PERMS for arm64, allowing the core code to manage the permissions of executable vmalloc regions more strictly - Slight performance improvement by keeping softirqs enabled while touching the FPSIMD/SVE state (kernel_neon_begin/end) - Expose a couple of ARMv8.5 features to user (HWCAP): CondM (new XAFLAG and AXFLAG instructions for floating point comparison flags manipulation) and FRINT (rounding floating point numbers to integers) - Re-instate ARM64_PSEUDO_NMI support which was previously marked as BROKEN due to some bugs (now fixed) - Improve parking of stopped CPUs and implement an arm64-specific panic_smp_self_stop() to avoid warning on not being able to stop secondary CPUs during panic - perf: enable the ARM Statistical Profiling Extensions (SPE) on ACPI platforms - perf: DDR performance monitor support for iMX8QXP - cache_line_size() can now be set from DT or ACPI/PPTT if provided to cope with a system cache info not exposed via the CPUID registers - Avoid warning on hardware cache line size greater than ARCH_DMA_MINALIGN if the system is fully coherent - arm64 do_page_fault() and hugetlb cleanups - Refactor set_pte_at() to avoid redundant READ_ONCE(*ptep) - Ignore ACPI 5.1 FADTs reported as 5.0 (infer from the 'arm_boot_flags' introduced in 5.1) - CONFIG_RANDOMIZE_BASE now enabled in defconfig - Allow the selection of ARM64_MODULE_PLTS, currently only done via RANDOMIZE_BASE (and an erratum workaround), allowing modules to spill over into the vmalloc area - Make ZONE_DMA32 configurable * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (54 commits) perf: arm_spe: Enable ACPI/Platform automatic module loading arm_pmu: acpi: spe: Add initial MADT/SPE probing ACPI/PPTT: Add function to return ACPI 6.3 Identical tokens ACPI/PPTT: Modify node flag detection to find last IDENTICAL x86/entry: Simplify _TIF_SYSCALL_EMU handling arm64: rename dump_instr as dump_kernel_instr arm64/mm: Drop [PTE|PMD]_TYPE_FAULT arm64: Implement panic_smp_self_stop() arm64: Improve parking of stopped CPUs arm64: Expose FRINT capabilities to userspace arm64: Expose ARMv8.5 CondM capability to userspace arm64: defconfig: enable CONFIG_RANDOMIZE_BASE arm64: ARM64_MODULES_PLTS must depend on MODULES arm64: bpf: do not allocate executable memory arm64/kprobes: set VM_FLUSH_RESET_PERMS on kprobe instruction pages arm64/mm: wire up CONFIG_ARCH_HAS_SET_DIRECT_MAP arm64: module: create module allocations without exec permissions arm64: Allow user selection of ARM64_MODULE_PLTS acpi/arm64: ignore 5.1 FADTs that are reported as 5.0 arm64: Allow selecting Pseudo-NMI again ...
183 lines
5.6 KiB
C
183 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/cacheflush.h
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*
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* Copyright (C) 1999-2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_CACHEFLUSH_H
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#define __ASM_CACHEFLUSH_H
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#include <linux/kgdb.h>
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#include <linux/mm.h>
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/*
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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*/
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#define PG_dcache_clean PG_arch_1
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/arm64/mm/cache.S implements these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive; start
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* addresses should be rounded down, end addresses up.
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*
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* See Documentation/core-api/cachetlb.rst for more information. Please note that
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* the implementation assumes non-aliasing VIPT D-cache and (aliasing)
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* VIPT I-cache.
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*
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* flush_cache_mm(mm)
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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* flush_icache_range(start, end)
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*
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* Ensure coherency between the I-cache and the D-cache in the
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* region described by start, end.
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* - start - virtual start address
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* - end - virtual end address
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*
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* invalidate_icache_range(start, end)
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*
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* Invalidate the I-cache in the region described by start, end.
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* - start - virtual start address
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* - end - virtual end address
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*
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* __flush_cache_user_range(start, end)
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*
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* Ensure coherency between the I-cache and the D-cache in the
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* region described by start, end.
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* - start - virtual start address
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* - end - virtual end address
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*
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* __flush_dcache_area(kaddr, size)
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*
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* Ensure that the data held in page is written back.
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* - kaddr - page address
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* - size - region size
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*/
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extern void __flush_icache_range(unsigned long start, unsigned long end);
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extern int invalidate_icache_range(unsigned long start, unsigned long end);
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extern void __flush_dcache_area(void *addr, size_t len);
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extern void __inval_dcache_area(void *addr, size_t len);
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extern void __clean_dcache_area_poc(void *addr, size_t len);
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extern void __clean_dcache_area_pop(void *addr, size_t len);
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extern void __clean_dcache_area_pou(void *addr, size_t len);
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extern long __flush_cache_user_range(unsigned long start, unsigned long end);
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extern void sync_icache_aliases(void *kaddr, unsigned long len);
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static inline void flush_icache_range(unsigned long start, unsigned long end)
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{
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__flush_icache_range(start, end);
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/*
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* IPI all online CPUs so that they undergo a context synchronization
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* event and are forced to refetch the new instructions.
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*/
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#ifdef CONFIG_KGDB
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/*
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* KGDB performs cache maintenance with interrupts disabled, so we
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* will deadlock trying to IPI the secondary CPUs. In theory, we can
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* set CACHE_FLUSH_IS_SAFE to 0 to avoid this known issue, but that
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* just means that KGDB will elide the maintenance altogether! As it
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* turns out, KGDB uses IPIs to round-up the secondary CPUs during
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* the patching operation, so we don't need extra IPIs here anyway.
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* In which case, add a KGDB-specific bodge and return early.
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*/
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if (kgdb_connected && irqs_disabled())
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return;
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#endif
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kick_all_cpus_sync();
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}
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static inline void flush_cache_mm(struct mm_struct *mm)
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{
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}
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static inline void flush_cache_page(struct vm_area_struct *vma,
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unsigned long user_addr, unsigned long pfn)
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{
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}
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static inline void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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}
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/*
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* Cache maintenance functions used by the DMA API. No to be used directly.
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*/
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extern void __dma_map_area(const void *, size_t, int);
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extern void __dma_unmap_area(const void *, size_t, int);
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extern void __dma_flush_area(const void *, size_t);
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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unsigned long, void *, const void *, unsigned long);
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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} while (0)
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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static inline void __flush_icache_all(void)
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{
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if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
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return;
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asm("ic ialluis");
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dsb(ish);
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}
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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/*
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* We don't appear to need to do anything here. In fact, if we did, we'd
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* duplicate cache flushing elsewhere performed by flush_dcache_page().
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*/
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#define flush_icache_page(vma,page) do { } while (0)
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/*
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* Not required on AArch64 (PIPT or VIPT non-aliasing D-cache).
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*/
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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}
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static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
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{
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}
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int set_memory_valid(unsigned long addr, int numpages, int enable);
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int set_direct_map_invalid_noflush(struct page *page);
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int set_direct_map_default_noflush(struct page *page);
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#endif
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