linux/arch/arm64/Kconfig.platforms
Arnd Bergmann 868a11b602 STM32 STM32MP25 for v6.5, round 1
Highlights:
 ----------
 
 STM32MP25 family is composed of 4 SoCs defined as following:
 
   -STM32MP251: common part composed of 1*Cortex-A35,
    common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
    parallel and DSI display, 1*ETH ...
 
   -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
    CAN-FD and LVDS display.
 
   -STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
   -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
 
   A second diversity layer exists for security features/A35 frequency:
   -STM32MP25xY, "Y" gives information:
     -Y = A means A35@1.2GHz + no cryp IP and no secure boot.
     -Y = C means A35@1.2GHz + cryp IP and secure boot.
     -Y = D means A35@1.5GHz + no cryp IP and no secure boot.
     -Y = F means A35@1.5GHz + cryp IP and secure boot.
 
 This PR adds the STM32MP257F EV1 board support. This board embeds a
 STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmSG5+AdHGFsZXhhbmRy
 ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIUXEA/4mb17fH6BUDc1wGHb
 kl7XJh8s9A98Wbjlei+fgZ6VfDRU1KuEkna/TJ+8QwBadb450RSPxCozWyaT94kq
 EeVHw2pyQELBA7T4Cu/3OzyD2dQj/hELbWKlUT5UedMibguxYb+IyxMqOrw29Ghb
 t5G1cfJknkbXQDKrEVDynUHoRcDIb3vLXhvL3Z8ExSDBaaVdhrpXyJow4fRBUgtY
 gqEnVJHOVHsu5k+Ah2/2SaMUpxfQIUduxFMsk7pAFiZU+nRQI03Cn6EKADCIgmS0
 1LZVhjfO15Tm5X2bDN+gHqC+3ASZGZqe4KkUF5RfIN+2K1Jo8CMCoezHga0y03Lb
 EN6PEoHhriqNs/2azFLTQbua0RzkdJxXNNWAG5I+I0qim6hicTV9YCkkxIQlhNxu
 K67BdvBEJrDNBYlkk4DDaiGRuPFSoitwYMnZqCrvLGtxtTbjrMjppCCvdJPrCGBr
 aY/1hLePnnxdBvCFKODKkiAT48gPjZoEhLrbegIY2XMqseciX4o9JZbXmnMVdpqD
 2l1M2xsyVe5Jxv8JRfnr6GfUj0FVIgxB8tUII7OpXxTGZN9MaOt/92DKTbvLdvma
 MwIOIMKB5QYFytCNwjFMI2LJopfiFJNUKk2Yd+WNWGaEG1LmdhTSIIROQBMDM5Zg
 xTR+DvbdtbgyTSSsuBDGw1UWnA==
 =WkNC
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSSC/wACgkQYKtH/8kJ
 UidpWhAAn9bQwdIJdetMmMiJuvFJIqPg48K9OmvEpEYCxAwVFuKTV+ddGDM2kLwB
 rinJ5R92FsCUBN54mPpfq75atuhZA8S3Od4N8jbjK7Geqq0MIUv6yaGYNyKJfDrx
 NO3+UzIpF17eqiXDTY4ZEdw+FfWJ1fr1rKN2DNyqIQDIibvOR8smuAE9suIdNsht
 0k0LOCk+PXRaNws6wIeXM71v42trb8S5UG02qQzet1qwsK7OXUc7xouTr6vQ7xMR
 H4NiuEL0XfkhsxsSLhbFSpWzRoVcKhhyZzibNu4l5npBvL0VZPyYrJOU7MAODy5D
 IWIS07/BNWrKx/XhCyz7w0ID2SsMGxAgGeOMx1eG3WT5953z5tWOqBgZGWrObQMO
 QR4F2h+f9InLblHEdLa+n1Nfm6SAgGEA+JnDDHSbuiH1t/g01wazxCAi6Awoxur6
 jv7iINiy2UauRs7/Fns0z1J0gag/8afxTYiEzBQSMdrE4zgaKKGtryoflUOXZe9W
 foXtU4+mRAExrZN/3gxYQyvvLxQF7vllCYtuzeUyJzpXuYwE5clpjjEn93txXtPr
 EjIS+fg3cgABaD26607ueGomQIdKxjWj/1tZSaut1yWs/zeuRjS15dT68IzzI0mK
 Qk1v6mLx+gdnOQv8mn5JfzOC8MTDBrAE53B6M+mI9nZrV3VhhhE=
 =fxHg
 -----END PGP SIGNATURE-----

Merge tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/newsoc

STM32 STM32MP25 for v6.5, round 1

Highlights:
----------

STM32MP25 family is composed of 4 SoCs defined as following:

  -STM32MP251: common part composed of 1*Cortex-A35,
   common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
   parallel and DSI display, 1*ETH ...

  -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
   CAN-FD and LVDS display.

  -STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
  -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).

  A second diversity layer exists for security features/A35 frequency:
  -STM32MP25xY, "Y" gives information:
    -Y = A means A35@1.2GHz + no cryp IP and no secure boot.
    -Y = C means A35@1.2GHz + cryp IP and secure boot.
    -Y = D means A35@1.5GHz + no cryp IP and no secure boot.
    -Y = F means A35@1.5GHz + cryp IP and secure boot.

This PR adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...

* tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (44 commits)
  MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
  arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
  arm64: dts: st: add stm32mp257f-ev1 board support
  dt-bindings: stm32: document stm32mp257f-ev1 board
  arm64: dts: st: introduce stm32mp25 pinctrl files
  arm64: dts: st: introduce stm32mp25 SoCs family
  arm64: introduce STM32 family on Armv8 architecture
  dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
  pinctrl: stm32: add stm32mp257 pinctrl support
  dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
  ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx
  ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2
  ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1
  ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems
  ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench
  ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc
  ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon
  ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1
  ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards
  ARM: dts: stm32: add vrefint support to adc2 on stm32mp15
  ...

Link: https://lore.kernel.org/r/080fc303-45c1-6cc0-4c5e-694e730896a6@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20 22:28:44 +02:00

378 lines
8.7 KiB
Plaintext

# SPDX-License-Identifier: GPL-2.0-only
menu "Platform selection"
config ARCH_ACTIONS
bool "Actions Semi Platforms"
select OWL_TIMER
select PINCTRL
help
This enables support for the Actions Semiconductor S900 SoC family.
config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select ARCH_HAS_RESET_CONTROLLER
select PINCTRL
select RESET_CONTROLLER
select SUN4I_TIMER
select SUN6I_R_INTC
select SUNXI_NMI_INTC
help
This enables support for Allwinner sunxi based SoCs like the A64.
config ARCH_ALPINE
bool "Annapurna Labs Alpine platform"
select ALPINE_MSI if PCI
help
This enables support for the Annapurna Labs Alpine
Soc family.
config ARCH_APPLE
bool "Apple Silicon SoC family"
select APPLE_AIC
help
This enables support for Apple's in-house ARM SoC family, starting
with the Apple M1.
menuconfig ARCH_BCM
bool "Broadcom SoC Support"
if ARCH_BCM
config ARCH_BCM2835
bool "Broadcom BCM2835 family"
select TIMER_OF
select GPIOLIB
select MFD_CORE
select PINCTRL
select PINCTRL_BCM2835
select ARM_AMBA
select ARM_GIC
select ARM_TIMER_SP804
help
This enables support for the Broadcom BCM2837 and BCM2711 SoC.
These SoCs are used in the Raspberry Pi 3 and 4 devices.
config ARCH_BCM_IPROC
bool "Broadcom iProc SoC Family"
select COMMON_CLK_IPROC
select GPIOLIB
select PINCTRL
help
This enables support for Broadcom iProc based SoCs
config ARCH_BCMBCA
bool "Broadcom Broadband Carrier Access (BCA) origin SoC"
select GPIOLIB
help
Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
BCA chipset.
This enables support for Broadcom BCA ARM-based broadband chipsets,
including the DSL, PON and Wireless family of chips.
config ARCH_BRCMSTB
bool "Broadcom Set-Top-Box SoCs"
select ARCH_HAS_RESET_CONTROLLER
select GENERIC_IRQ_CHIP
select PINCTRL
help
This enables support for Broadcom's ARMv8 Set Top Box SoCs
endif
config ARCH_BERLIN
bool "Marvell Berlin SoC Family"
select DW_APB_ICTL
select DW_APB_TIMER_OF
select GPIOLIB
select PINCTRL
help
This enables support for Marvell Berlin SoC Family
config ARCH_BITMAIN
bool "Bitmain SoC Platforms"
help
This enables support for the Bitmain SoC Family.
config ARCH_EXYNOS
bool "Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG
select CLKSRC_EXYNOS_MCT
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
select EXYNOS_PMU
select PINCTRL
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM
select SOC_SAMSUNG
help
This enables support for ARMv8 based Samsung Exynos SoC family.
config ARCH_SPARX5
bool "Microchip Sparx5 SoC family"
select PINCTRL
select DW_APB_TIMER_OF
help
This enables support for the Microchip Sparx5 ARMv8-based
SoC family of TSN-capable gigabit switches.
The SparX-5 Ethernet switch family provides a rich set of
switching features such as advanced TCAM-based VLAN and QoS
processing enabling delivery of differentiated services, and
security through TCAM-based frame processing using versatile
content aware processor (VCAP).
config ARCH_K3
bool "Texas Instruments Inc. K3 multicore SoC architecture"
select PM_GENERIC_DOMAINS if PM
select MAILBOX
select SOC_TI
select TI_MESSAGE_MANAGER
select TI_SCI_PROTOCOL
select TI_SCI_INTR_IRQCHIP
select TI_SCI_INTA_IRQCHIP
select TI_K3_SOCINFO
help
This enables support for Texas Instruments' K3 multicore SoC
architecture.
config ARCH_LG1K
bool "LG Electronics LG1K SoC Family"
help
This enables support for LG Electronics LG1K SoC Family
config ARCH_HISI
bool "Hisilicon SoC Family"
select ARM_TIMER_SP804
select HISILICON_IRQ_MBIGEN if PCI
select PINCTRL
help
This enables support for Hisilicon ARMv8 SoC family
config ARCH_KEEMBAY
bool "Keem Bay SoC"
help
This enables support for Intel Movidius SoC code-named Keem Bay.
config ARCH_MEDIATEK
bool "MediaTek SoC Family"
select ARM_GIC
select PINCTRL
select MTK_TIMER
help
This enables support for MediaTek MT27xx, MT65xx, MT76xx
& MT81xx ARMv8 SoCs
config ARCH_MESON
bool "Amlogic Platforms"
help
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
config ARCH_MVEBU
bool "Marvell EBU SoC Family"
select ARMADA_AP806_SYSCON
select ARMADA_CP110_SYSCON
select ARMADA_37XX_CLK
select GPIOLIB
select GPIOLIB_IRQCHIP
select MVEBU_GICP
select MVEBU_ICU
select MVEBU_ODMI
select MVEBU_PIC
select MVEBU_SEI
select OF_GPIO
select PINCTRL
select PINCTRL_ARMADA_37XX
select PINCTRL_ARMADA_AP806
select PINCTRL_ARMADA_CP110
select PINCTRL_AC5
help
This enables support for Marvell EBU family, including:
- Armada 3700 SoC Family
- Armada 7K SoC Family
- Armada 8K SoC Family
- 98DX2530 SoC Family
menuconfig ARCH_NXP
bool "NXP SoC support"
if ARCH_NXP
config ARCH_LAYERSCAPE
bool "Freescale Layerscape SoC family"
select EDAC_SUPPORT
help
This enables support for the Freescale Layerscape SoC family.
config ARCH_MXC
bool "NXP i.MX SoC family"
select ARM64_ERRATUM_843419
select ARM64_ERRATUM_845719 if COMPAT
select IMX_GPCV2
select IMX_GPCV2_PM_DOMAINS
select PM
select PM_GENERIC_DOMAINS
select SOC_BUS
select TIMER_IMX_SYS_CTR
help
This enables support for the ARMv8 based SoCs in the
NXP i.MX family.
config ARCH_S32
bool "NXP S32 SoC Family"
help
This enables support for the NXP S32 family of processors.
endif
config ARCH_MA35
bool "Nuvoton MA35 Architecture"
select GPIOLIB
select PINCTRL
select RESET_CONTROLLER
help
This enables support for the ARMv8 based Nuvoton MA35 series SoCs.
config ARCH_NPCM
bool "Nuvoton NPCM Architecture"
select PINCTRL
select GPIOLIB
select NPCM7XX_TIMER
select RESET_CONTROLLER
select MFD_SYSCON
help
General support for NPCM8xx BMC (Arbel).
Nuvoton NPCM8xx BMC based on the Cortex A35.
config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
select PINCTRL
help
This enables support for the ARMv8 based Qualcomm chipsets.
config ARCH_REALTEK
bool "Realtek Platforms"
select RESET_CONTROLLER
help
This enables support for the ARMv8 based Realtek chipsets,
like the RTD1295.
config ARCH_RENESAS
bool "Renesas SoC Platforms"
help
This enables support for the ARMv8 based Renesas SoCs.
config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER
select PINCTRL
select PM
select ROCKCHIP_TIMER
help
This enables support for the ARMv8 based Rockchip chipsets,
like the RK3368.
config ARCH_SEATTLE
bool "AMD Seattle SoC Family"
help
This enables support for AMD Seattle SOC Family
config ARCH_INTEL_SOCFPGA
bool "Intel's SoCFPGA ARMv8 Families"
help
This enables support for Intel's SoCFPGA ARMv8 families:
Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
Agilex and eASIC N5X.
config ARCH_STM32
bool "STMicroelectronics STM32 SoC Family"
select GPIOLIB
select PINCTRL
select PINCTRL_STM32MP257
select ARM_SMC_MBOX
select ARM_SCMI_PROTOCOL
select COMMON_CLK_SCMI
help
This enables support for ARMv8 based STMicroelectronics
STM32 family, including:
- STM32MP25:
- STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
config ARCH_SYNQUACER
bool "Socionext SynQuacer SoC Family"
select IRQ_FASTEOI_HIERARCHY_HANDLERS
config ARCH_TEGRA
bool "NVIDIA Tegra SoC Family"
select ARCH_HAS_RESET_CONTROLLER
select ARM_GIC_PM
select CLKSRC_MMIO
select TIMER_OF
select GPIOLIB
select PINCTRL
select PM
select PM_GENERIC_DOMAINS
select RESET_CONTROLLER
help
This enables support for the NVIDIA Tegra SoC family.
config ARCH_TESLA_FSD
bool "Tesla platform"
depends on ARCH_EXYNOS
help
Support for ARMv8 based Tesla platforms.
config ARCH_SPRD
bool "Spreadtrum SoC platform"
help
Support for Spreadtrum ARM based SoCs
config ARCH_THUNDER
bool "Cavium Inc. Thunder SoC Family"
help
This enables support for Cavium's Thunder Family of SoCs.
config ARCH_THUNDER2
bool "Cavium ThunderX2 Server Processors"
select GPIOLIB
help
This enables support for Cavium's ThunderX2 CN99XX family of
server processors.
config ARCH_UNIPHIER
bool "Socionext UniPhier SoC Family"
select ARCH_HAS_RESET_CONTROLLER
select PINCTRL
select RESET_CONTROLLER
help
This enables support for Socionext UniPhier SoC family.
config ARCH_VEXPRESS
bool "ARMv8 software model (Versatile Express)"
select GPIOLIB
select PM
select PM_GENERIC_DOMAINS
help
This enables support for the ARMv8 software model (Versatile
Express).
config ARCH_VISCONTI
bool "Toshiba Visconti SoC Family"
select PINCTRL
select PINCTRL_VISCONTI
help
This enables support for Toshiba Visconti SoCs Family.
config ARCH_XGENE
bool "AppliedMicro X-Gene SOC Family"
help
This enables support for AppliedMicro X-Gene SOC Family
config ARCH_ZYNQMP
bool "Xilinx ZynqMP Family"
help
This enables support for Xilinx ZynqMP Family
endmenu # "Platform selection"