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162874d5f5
Add support to dump the HDMI wrapper, core, PLL and PHY registers through debugfs. Signed-off-by: Mythri P K <mythripk@ti.com> [tomi.valkeinen@ti.com: updated the description] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/*
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* ti_hdmi.h
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*
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* HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor.
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TI_HDMI_H
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#define _TI_HDMI_H
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struct hdmi_ip_data;
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enum hdmi_pll_pwr {
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HDMI_PLLPWRCMD_ALLOFF = 0,
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HDMI_PLLPWRCMD_PLLONLY = 1,
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HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
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HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
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};
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enum hdmi_core_hdmi_dvi {
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HDMI_DVI = 0,
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HDMI_HDMI = 1
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};
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enum hdmi_clk_refsel {
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HDMI_REFSEL_PCLK = 0,
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HDMI_REFSEL_REF1 = 1,
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HDMI_REFSEL_REF2 = 2,
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HDMI_REFSEL_SYSCLK = 3
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};
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struct hdmi_video_timings {
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u16 x_res;
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u16 y_res;
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/* Unit: KHz */
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u32 pixel_clock;
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u16 hsw;
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u16 hfp;
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u16 hbp;
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u16 vsw;
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u16 vfp;
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u16 vbp;
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};
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/* HDMI timing structure */
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struct hdmi_timings {
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struct hdmi_video_timings timings;
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int vsync_pol;
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int hsync_pol;
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};
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struct hdmi_cm {
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int code;
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int mode;
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};
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struct hdmi_config {
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struct hdmi_timings timings;
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u16 interlace;
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struct hdmi_cm cm;
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};
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/* HDMI PLL structure */
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struct hdmi_pll_info {
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u16 regn;
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u16 regm;
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u32 regmf;
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u16 regm2;
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u16 regsd;
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u16 dcofreq;
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enum hdmi_clk_refsel refsel;
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};
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struct ti_hdmi_ip_ops {
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void (*video_configure)(struct hdmi_ip_data *ip_data);
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int (*phy_enable)(struct hdmi_ip_data *ip_data);
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void (*phy_disable)(struct hdmi_ip_data *ip_data);
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int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len);
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bool (*detect)(struct hdmi_ip_data *ip_data);
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int (*pll_enable)(struct hdmi_ip_data *ip_data);
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void (*pll_disable)(struct hdmi_ip_data *ip_data);
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void (*video_enable)(struct hdmi_ip_data *ip_data, bool start);
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void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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};
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struct hdmi_ip_data {
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void __iomem *base_wp; /* HDMI wrapper */
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unsigned long core_sys_offset;
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unsigned long core_av_offset;
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unsigned long pll_offset;
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unsigned long phy_offset;
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const struct ti_hdmi_ip_ops *ops;
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struct hdmi_config cfg;
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struct hdmi_pll_info pll_data;
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};
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int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
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int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);
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bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
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int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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#endif
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