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a4ff8e7a71
Per PCIe r6.0, sec 6.30.1, a data object Length of 0x0 indicates 2^18
DWORDs (256K DW or 1MB) being transferred. Adjust the value of data object
length for this case on both sending side and receiving side.
Don't bother checking whether Length is greater than SZ_1M because all
values of the 18-bit Length field are valid, and it is impossible to
represent anything larger than SZ_1M:
0x00000 256K DW (1M bytes)
0x00001 1 DW (4 bytes)
...
0x3ffff 256K-1 DW (1M - 4 bytes)
[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20221116015637.3299664-1-ming4.li@intel.com
Fixes: 9d24322e88
("PCI/DOE: Add DOE mailbox support functions")
Signed-off-by: Li Ming <ming4.li@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Lukas Wunner <lukas@wunner.de>
Cc: stable@vger.kernel.org # v6.0+
549 lines
14 KiB
C
549 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Data Object Exchange
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* PCIe r6.0, sec 6.30 DOE
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*
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* Copyright (C) 2021 Huawei
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* Jonathan Cameron <Jonathan.Cameron@huawei.com>
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*
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* Copyright (C) 2022 Intel Corporation
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* Ira Weiny <ira.weiny@intel.com>
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*/
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#define dev_fmt(fmt) "DOE: " fmt
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/jiffies.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/pci-doe.h>
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#include <linux/workqueue.h>
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#define PCI_DOE_PROTOCOL_DISCOVERY 0
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/* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */
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#define PCI_DOE_TIMEOUT HZ
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#define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128)
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#define PCI_DOE_FLAG_CANCEL 0
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#define PCI_DOE_FLAG_DEAD 1
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/* Max data object length is 2^18 dwords */
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#define PCI_DOE_MAX_LENGTH (1 << 18)
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/**
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* struct pci_doe_mb - State for a single DOE mailbox
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*
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* This state is used to manage a single DOE mailbox capability. All fields
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* should be considered opaque to the consumers and the structure passed into
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* the helpers below after being created by devm_pci_doe_create()
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*
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* @pdev: PCI device this mailbox belongs to
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* @cap_offset: Capability offset
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* @prots: Array of protocols supported (encoded as long values)
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* @wq: Wait queue for work item
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* @work_queue: Queue of pci_doe_work items
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* @flags: Bit array of PCI_DOE_FLAG_* flags
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*/
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struct pci_doe_mb {
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struct pci_dev *pdev;
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u16 cap_offset;
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struct xarray prots;
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wait_queue_head_t wq;
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struct workqueue_struct *work_queue;
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unsigned long flags;
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};
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static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout)
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{
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if (wait_event_timeout(doe_mb->wq,
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test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags),
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timeout))
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return -EIO;
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return 0;
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}
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static void pci_doe_write_ctrl(struct pci_doe_mb *doe_mb, u32 val)
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{
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struct pci_dev *pdev = doe_mb->pdev;
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int offset = doe_mb->cap_offset;
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pci_write_config_dword(pdev, offset + PCI_DOE_CTRL, val);
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}
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static int pci_doe_abort(struct pci_doe_mb *doe_mb)
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{
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struct pci_dev *pdev = doe_mb->pdev;
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int offset = doe_mb->cap_offset;
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unsigned long timeout_jiffies;
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pci_dbg(pdev, "[%x] Issuing Abort\n", offset);
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timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
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pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_ABORT);
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do {
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int rc;
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u32 val;
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rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
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if (rc)
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return rc;
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pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
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/* Abort success! */
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if (!FIELD_GET(PCI_DOE_STATUS_ERROR, val) &&
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!FIELD_GET(PCI_DOE_STATUS_BUSY, val))
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return 0;
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} while (!time_after(jiffies, timeout_jiffies));
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/* Abort has timed out and the MB is dead */
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pci_err(pdev, "[%x] ABORT timed out\n", offset);
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return -EIO;
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}
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static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
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struct pci_doe_task *task)
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{
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struct pci_dev *pdev = doe_mb->pdev;
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int offset = doe_mb->cap_offset;
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size_t length;
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u32 val;
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int i;
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/*
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* Check the DOE busy bit is not set. If it is set, this could indicate
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* someone other than Linux (e.g. firmware) is using the mailbox. Note
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* it is expected that firmware and OS will negotiate access rights via
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* an, as yet to be defined, method.
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*/
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pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
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if (FIELD_GET(PCI_DOE_STATUS_BUSY, val))
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return -EBUSY;
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if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
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return -EIO;
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/* Length is 2 DW of header + length of payload in DW */
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length = 2 + task->request_pl_sz / sizeof(u32);
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if (length > PCI_DOE_MAX_LENGTH)
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return -EIO;
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if (length == PCI_DOE_MAX_LENGTH)
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length = 0;
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/* Write DOE Header */
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val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->prot.vid) |
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FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->prot.type);
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pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val);
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pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
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FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
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length));
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for (i = 0; i < task->request_pl_sz / sizeof(u32); i++)
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pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
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task->request_pl[i]);
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pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_GO);
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return 0;
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}
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static bool pci_doe_data_obj_ready(struct pci_doe_mb *doe_mb)
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{
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struct pci_dev *pdev = doe_mb->pdev;
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int offset = doe_mb->cap_offset;
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u32 val;
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pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
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if (FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val))
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return true;
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return false;
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}
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static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
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{
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struct pci_dev *pdev = doe_mb->pdev;
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int offset = doe_mb->cap_offset;
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size_t length, payload_length;
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u32 val;
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int i;
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/* Read the first dword to get the protocol */
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pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
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if ((FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val) != task->prot.vid) ||
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(FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val) != task->prot.type)) {
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dev_err_ratelimited(&pdev->dev, "[%x] expected [VID, Protocol] = [%04x, %02x], got [%04x, %02x]\n",
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doe_mb->cap_offset, task->prot.vid, task->prot.type,
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FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val),
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FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val));
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return -EIO;
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}
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pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
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/* Read the second dword to get the length */
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pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
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pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
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length = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, val);
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/* A value of 0x0 indicates max data object length */
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if (!length)
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length = PCI_DOE_MAX_LENGTH;
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if (length < 2)
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return -EIO;
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/* First 2 dwords have already been read */
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length -= 2;
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payload_length = min(length, task->response_pl_sz / sizeof(u32));
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/* Read the rest of the response payload */
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for (i = 0; i < payload_length; i++) {
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pci_read_config_dword(pdev, offset + PCI_DOE_READ,
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&task->response_pl[i]);
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/* Prior to the last ack, ensure Data Object Ready */
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if (i == (payload_length - 1) && !pci_doe_data_obj_ready(doe_mb))
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return -EIO;
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pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
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}
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/* Flush excess length */
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for (; i < length; i++) {
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pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
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pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
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}
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/* Final error check to pick up on any since Data Object Ready */
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pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
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if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
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return -EIO;
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return min(length, task->response_pl_sz / sizeof(u32)) * sizeof(u32);
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}
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static void signal_task_complete(struct pci_doe_task *task, int rv)
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{
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task->rv = rv;
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task->complete(task);
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}
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static void signal_task_abort(struct pci_doe_task *task, int rv)
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{
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struct pci_doe_mb *doe_mb = task->doe_mb;
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struct pci_dev *pdev = doe_mb->pdev;
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if (pci_doe_abort(doe_mb)) {
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/*
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* If the device can't process an abort; set the mailbox dead
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* - no more submissions
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*/
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pci_err(pdev, "[%x] Abort failed marking mailbox dead\n",
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doe_mb->cap_offset);
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set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags);
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}
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signal_task_complete(task, rv);
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}
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static void doe_statemachine_work(struct work_struct *work)
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{
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struct pci_doe_task *task = container_of(work, struct pci_doe_task,
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work);
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struct pci_doe_mb *doe_mb = task->doe_mb;
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struct pci_dev *pdev = doe_mb->pdev;
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int offset = doe_mb->cap_offset;
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unsigned long timeout_jiffies;
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u32 val;
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int rc;
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if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags)) {
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signal_task_complete(task, -EIO);
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return;
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}
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/* Send request */
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rc = pci_doe_send_req(doe_mb, task);
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if (rc) {
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/*
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* The specification does not provide any guidance on how to
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* resolve conflicting requests from other entities.
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* Furthermore, it is likely that busy will not be detected
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* most of the time. Flag any detection of status busy with an
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* error.
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*/
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if (rc == -EBUSY)
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dev_err_ratelimited(&pdev->dev, "[%x] busy detected; another entity is sending conflicting requests\n",
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offset);
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signal_task_abort(task, rc);
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return;
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}
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timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
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/* Poll for response */
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retry_resp:
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pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
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if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
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signal_task_abort(task, -EIO);
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return;
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}
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if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) {
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if (time_after(jiffies, timeout_jiffies)) {
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signal_task_abort(task, -EIO);
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return;
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}
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rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
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if (rc) {
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signal_task_abort(task, rc);
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return;
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}
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goto retry_resp;
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}
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rc = pci_doe_recv_resp(doe_mb, task);
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if (rc < 0) {
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signal_task_abort(task, rc);
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return;
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}
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signal_task_complete(task, rc);
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}
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static void pci_doe_task_complete(struct pci_doe_task *task)
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{
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complete(task->private);
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}
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static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid,
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u8 *protocol)
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{
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u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX,
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*index);
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u32 response_pl;
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DECLARE_COMPLETION_ONSTACK(c);
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struct pci_doe_task task = {
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.prot.vid = PCI_VENDOR_ID_PCI_SIG,
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.prot.type = PCI_DOE_PROTOCOL_DISCOVERY,
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.request_pl = &request_pl,
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.request_pl_sz = sizeof(request_pl),
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.response_pl = &response_pl,
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.response_pl_sz = sizeof(response_pl),
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.complete = pci_doe_task_complete,
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.private = &c,
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};
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int rc;
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rc = pci_doe_submit_task(doe_mb, &task);
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if (rc < 0)
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return rc;
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wait_for_completion(&c);
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if (task.rv != sizeof(response_pl))
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return -EIO;
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*vid = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID, response_pl);
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*protocol = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL,
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response_pl);
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*index = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX,
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response_pl);
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return 0;
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}
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static void *pci_doe_xa_prot_entry(u16 vid, u8 prot)
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{
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return xa_mk_value((vid << 8) | prot);
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}
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static int pci_doe_cache_protocols(struct pci_doe_mb *doe_mb)
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{
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u8 index = 0;
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u8 xa_idx = 0;
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do {
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int rc;
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u16 vid;
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u8 prot;
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rc = pci_doe_discovery(doe_mb, &index, &vid, &prot);
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if (rc)
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return rc;
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pci_dbg(doe_mb->pdev,
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"[%x] Found protocol %d vid: %x prot: %x\n",
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doe_mb->cap_offset, xa_idx, vid, prot);
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rc = xa_insert(&doe_mb->prots, xa_idx++,
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pci_doe_xa_prot_entry(vid, prot), GFP_KERNEL);
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if (rc)
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return rc;
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} while (index);
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return 0;
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}
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static void pci_doe_xa_destroy(void *mb)
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{
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struct pci_doe_mb *doe_mb = mb;
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xa_destroy(&doe_mb->prots);
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}
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static void pci_doe_destroy_workqueue(void *mb)
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{
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struct pci_doe_mb *doe_mb = mb;
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destroy_workqueue(doe_mb->work_queue);
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}
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static void pci_doe_flush_mb(void *mb)
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{
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struct pci_doe_mb *doe_mb = mb;
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/* Stop all pending work items from starting */
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set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags);
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/* Cancel an in progress work item, if necessary */
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set_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags);
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wake_up(&doe_mb->wq);
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/* Flush all work items */
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flush_workqueue(doe_mb->work_queue);
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}
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/**
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* pcim_doe_create_mb() - Create a DOE mailbox object
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*
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* @pdev: PCI device to create the DOE mailbox for
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* @cap_offset: Offset of the DOE mailbox
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*
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* Create a single mailbox object to manage the mailbox protocol at the
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* cap_offset specified.
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*
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* RETURNS: created mailbox object on success
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* ERR_PTR(-errno) on failure
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*/
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struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset)
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{
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struct pci_doe_mb *doe_mb;
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struct device *dev = &pdev->dev;
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int rc;
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doe_mb = devm_kzalloc(dev, sizeof(*doe_mb), GFP_KERNEL);
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if (!doe_mb)
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return ERR_PTR(-ENOMEM);
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doe_mb->pdev = pdev;
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doe_mb->cap_offset = cap_offset;
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init_waitqueue_head(&doe_mb->wq);
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xa_init(&doe_mb->prots);
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rc = devm_add_action(dev, pci_doe_xa_destroy, doe_mb);
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if (rc)
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return ERR_PTR(rc);
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doe_mb->work_queue = alloc_ordered_workqueue("%s %s DOE [%x]", 0,
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dev_driver_string(&pdev->dev),
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pci_name(pdev),
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doe_mb->cap_offset);
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if (!doe_mb->work_queue) {
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pci_err(pdev, "[%x] failed to allocate work queue\n",
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doe_mb->cap_offset);
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return ERR_PTR(-ENOMEM);
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}
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rc = devm_add_action_or_reset(dev, pci_doe_destroy_workqueue, doe_mb);
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if (rc)
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return ERR_PTR(rc);
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/* Reset the mailbox by issuing an abort */
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rc = pci_doe_abort(doe_mb);
|
|
if (rc) {
|
|
pci_err(pdev, "[%x] failed to reset mailbox with abort command : %d\n",
|
|
doe_mb->cap_offset, rc);
|
|
return ERR_PTR(rc);
|
|
}
|
|
|
|
/*
|
|
* The state machine and the mailbox should be in sync now;
|
|
* Set up mailbox flush prior to using the mailbox to query protocols.
|
|
*/
|
|
rc = devm_add_action_or_reset(dev, pci_doe_flush_mb, doe_mb);
|
|
if (rc)
|
|
return ERR_PTR(rc);
|
|
|
|
rc = pci_doe_cache_protocols(doe_mb);
|
|
if (rc) {
|
|
pci_err(pdev, "[%x] failed to cache protocols : %d\n",
|
|
doe_mb->cap_offset, rc);
|
|
return ERR_PTR(rc);
|
|
}
|
|
|
|
return doe_mb;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pcim_doe_create_mb);
|
|
|
|
/**
|
|
* pci_doe_supports_prot() - Return if the DOE instance supports the given
|
|
* protocol
|
|
* @doe_mb: DOE mailbox capability to query
|
|
* @vid: Protocol Vendor ID
|
|
* @type: Protocol type
|
|
*
|
|
* RETURNS: True if the DOE mailbox supports the protocol specified
|
|
*/
|
|
bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
|
|
{
|
|
unsigned long index;
|
|
void *entry;
|
|
|
|
/* The discovery protocol must always be supported */
|
|
if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_PROTOCOL_DISCOVERY)
|
|
return true;
|
|
|
|
xa_for_each(&doe_mb->prots, index, entry)
|
|
if (entry == pci_doe_xa_prot_entry(vid, type))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_doe_supports_prot);
|
|
|
|
/**
|
|
* pci_doe_submit_task() - Submit a task to be processed by the state machine
|
|
*
|
|
* @doe_mb: DOE mailbox capability to submit to
|
|
* @task: task to be queued
|
|
*
|
|
* Submit a DOE task (request/response) to the DOE mailbox to be processed.
|
|
* Returns upon queueing the task object. If the queue is full this function
|
|
* will sleep until there is room in the queue.
|
|
*
|
|
* task->complete will be called when the state machine is done processing this
|
|
* task.
|
|
*
|
|
* Excess data will be discarded.
|
|
*
|
|
* RETURNS: 0 when task has been successfully queued, -ERRNO on error
|
|
*/
|
|
int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
|
|
{
|
|
if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* DOE requests must be a whole number of DW and the response needs to
|
|
* be big enough for at least 1 DW
|
|
*/
|
|
if (task->request_pl_sz % sizeof(u32) ||
|
|
task->response_pl_sz < sizeof(u32))
|
|
return -EINVAL;
|
|
|
|
if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags))
|
|
return -EIO;
|
|
|
|
task->doe_mb = doe_mb;
|
|
INIT_WORK(&task->work, doe_statemachine_work);
|
|
queue_work(doe_mb->work_queue, &task->work);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_doe_submit_task);
|