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433bcf6737
- switch xtensa arch to the generic noncoherent direct mapping operations; - add support for DMA_ATTR_NO_KERNEL_MAPPING attribute; - clean up users of platform/hardware.h in generic Xtensa code; - fix assembly cache maintenance code for long cache lines; - rework noMMU cache attributes initialization; - add big-endian HiFi2 test_kc705_be CPU variant. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAlt7KZATHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRKZyD/9hJ9L4qNa+E1UaEGxuLcQP98HtwXDV 140/v8m6pw3leblyIGiFypnjHZidol74YQ17DDzckEuSZLa13H8EcB1c/oNTjKve 65/Jz8M9KPaASIRgdcqMp7IZt4wGSVV4mOkwodtmJBefpQa6Y2gHXhmLiIK27WVR m/J6xVYCgTa93e+Tjcn1x+Y1NbpzFlRV2MTfMZLD8hxtUYmt+iPPUtWMKjn3bBJI ps0cor1yAvbGQ6Bg95yal/Wd6pHfnqMs3is3BqW4ZC0LYwch+JT5Btbh2SVYOrX+ ea7iAy3f8eH866SAGb4B3JOTwtaSFL84QFVp/UXY0tZk2IDr3YGiBOV2pic2zSao 3td3y/ZTROcW+18gUip5VtaSKbVZ1yWbut9MnbW2i79VoXAx3XwA4Mo9cBYTQUaj rAB/B62ACcQt0OUG4jvamGdmIgF+FF6Pr4nqJ9iFfIoj4e+UxUMH9U2Wd8H/7WCl rWYJEIkGE8z7bkQw2izXfVc3wBSc2c6z3UjEMijU8I7/V3Yg+WKcAgaWsHd34IDS bURrTWqPN4plXbuuQHrRinHlFUjsx6iZk3ClXn7NTFPx2G69aPOoiHxz0tV9C9Tp fwRHMy5wTeKjfbz4Gd2LlHjDz6kO53DVOsb09B12lVPPTvtLOLbI0G4gHzOw3QVk WwxmbsAv1/NaLA== =osJd -----END PGP SIGNATURE----- Merge tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa Pull Xtensa updates from Max Filippov: - switch xtensa arch to the generic noncoherent direct mapping operations - add support for DMA_ATTR_NO_KERNEL_MAPPING attribute - clean up users of platform/hardware.h in generic Xtensa code - fix assembly cache maintenance code for long cache lines - rework noMMU cache attributes initialization - add big-endian HiFi2 test_kc705_be CPU variant * tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: add test_kc705_be variant xtensa: clean up boot-elf/bootstrap.S xtensa: make bootparam parsing optional xtensa: drop variant IRQ support xtensa: drop unneeded platform/hardware.h headers xtensa: move PLATFORM_NR_IRQS to Kconfig xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START xtensa: drop unused {CONFIG,PLATFORM}_DEFAULT_MEM_SIZE xtensa: rework noMMU cache attributes initialization xtensa: increase ranges in ___invalidate_{i,d}cache_all xtensa: limit offsets in __loop_cache_{all,page} xtensa: platform-specific handling of coherent memory xtensa: support DMA_ATTR_NO_KERNEL_MAPPING attribute xtensa: use generic dma_noncoherent_ops
213 lines
5.0 KiB
C
213 lines
5.0 KiB
C
/*
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* DMA coherent memory allocation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Copyright (C) 2002 - 2005 Tensilica Inc.
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* Copyright (C) 2015 Cadence Design Systems Inc.
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*
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* Based on version for i386.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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*/
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#include <linux/dma-contiguous.h>
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#include <linux/dma-noncoherent.h>
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#include <linux/dma-direct.h>
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#include <linux/gfp.h>
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#include <linux/highmem.h>
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#include <linux/mm.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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#include <asm/platform.h>
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static void do_cache_op(phys_addr_t paddr, size_t size,
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void (*fn)(unsigned long, unsigned long))
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{
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unsigned long off = paddr & (PAGE_SIZE - 1);
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unsigned long pfn = PFN_DOWN(paddr);
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struct page *page = pfn_to_page(pfn);
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if (!PageHighMem(page))
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fn((unsigned long)phys_to_virt(paddr), size);
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else
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while (size > 0) {
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size_t sz = min_t(size_t, size, PAGE_SIZE - off);
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void *vaddr = kmap_atomic(page);
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fn((unsigned long)vaddr + off, sz);
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kunmap_atomic(vaddr);
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off = 0;
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++page;
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size -= sz;
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}
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}
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void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_BIDIRECTIONAL:
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case DMA_FROM_DEVICE:
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do_cache_op(paddr, size, __invalidate_dcache_range);
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break;
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case DMA_NONE:
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BUG();
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break;
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default:
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break;
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}
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}
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void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_BIDIRECTIONAL:
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case DMA_TO_DEVICE:
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if (XCHAL_DCACHE_IS_WRITEBACK)
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do_cache_op(paddr, size, __flush_dcache_range);
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break;
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case DMA_NONE:
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BUG();
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break;
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default:
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break;
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}
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}
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#ifdef CONFIG_MMU
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bool platform_vaddr_cached(const void *p)
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{
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unsigned long addr = (unsigned long)p;
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return addr >= XCHAL_KSEG_CACHED_VADDR &&
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addr - XCHAL_KSEG_CACHED_VADDR < XCHAL_KSEG_SIZE;
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}
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bool platform_vaddr_uncached(const void *p)
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{
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unsigned long addr = (unsigned long)p;
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return addr >= XCHAL_KSEG_BYPASS_VADDR &&
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addr - XCHAL_KSEG_BYPASS_VADDR < XCHAL_KSEG_SIZE;
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}
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void *platform_vaddr_to_uncached(void *p)
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{
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return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
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}
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void *platform_vaddr_to_cached(void *p)
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{
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return p + XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR;
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}
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#else
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bool __attribute__((weak)) platform_vaddr_cached(const void *p)
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{
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WARN_ONCE(1, "Default %s implementation is used\n", __func__);
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return true;
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}
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bool __attribute__((weak)) platform_vaddr_uncached(const void *p)
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{
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WARN_ONCE(1, "Default %s implementation is used\n", __func__);
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return false;
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}
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void __attribute__((weak)) *platform_vaddr_to_uncached(void *p)
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{
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WARN_ONCE(1, "Default %s implementation is used\n", __func__);
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return p;
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}
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void __attribute__((weak)) *platform_vaddr_to_cached(void *p)
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{
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WARN_ONCE(1, "Default %s implementation is used\n", __func__);
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return p;
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}
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#endif
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/*
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* Note: We assume that the full memory space is always mapped to 'kseg'
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* Otherwise we have to use page attributes (not implemented).
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*/
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void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
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gfp_t flag, unsigned long attrs)
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{
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unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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struct page *page = NULL;
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/* ignore region speicifiers */
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flag &= ~(__GFP_DMA | __GFP_HIGHMEM);
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if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
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flag |= GFP_DMA;
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if (gfpflags_allow_blocking(flag))
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page = dma_alloc_from_contiguous(dev, count, get_order(size),
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flag & __GFP_NOWARN);
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if (!page)
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page = alloc_pages(flag, get_order(size));
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if (!page)
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return NULL;
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*handle = phys_to_dma(dev, page_to_phys(page));
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if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
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return page;
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}
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#ifdef CONFIG_MMU
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if (PageHighMem(page)) {
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void *p;
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p = dma_common_contiguous_remap(page, size, VM_MAP,
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pgprot_noncached(PAGE_KERNEL),
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__builtin_return_address(0));
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if (!p) {
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if (!dma_release_from_contiguous(dev, page, count))
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__free_pages(page, get_order(size));
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}
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return p;
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}
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#endif
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BUG_ON(!platform_vaddr_cached(page_address(page)));
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__invalidate_dcache_range((unsigned long)page_address(page), size);
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return platform_vaddr_to_uncached(page_address(page));
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}
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void arch_dma_free(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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struct page *page;
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if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
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page = vaddr;
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} else if (platform_vaddr_uncached(vaddr)) {
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page = virt_to_page(platform_vaddr_to_cached(vaddr));
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} else {
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#ifdef CONFIG_MMU
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dma_common_free_remap(vaddr, size, VM_MAP);
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#endif
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page = pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_handle)));
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}
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if (!dma_release_from_contiguous(dev, page, count))
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__free_pages(page, get_order(size));
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}
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