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Tegra already supports the common clock framework, but had issues: 1) The clock driver was located in arch/arm/mach-tegra/ rather than drivers/clk/. 2) A single "Tegra clock" type was implemented, rather than separate clock types for PLL, mux, divider, ... type in HW. 3) Clock lookups by device drivers were still driven by device name and connection ID, rather than through device tree. This pull request solves all three issues. This required some DT changes to add clocks properties, and driver changes to request clocks more "correctly". Finally, this rework allows all AUXDATA to be removed from Tegra board files, and various duplicate clock lookup entries to be removed from the driver. This pull request is based on the previous pull request, with tag tegra-for-3.9-cleanup. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRCYtBAAoJEMzrak5tbycxKb8P/0cXt2X7mPfoApWV96bI2c9h VE1wZYREcq0Au3hiNuMmPp1Nwous2zvrXRKXMvLoQi42KwpvZlFjlyn8+xACKmxO okSJ+aXETzlGh85l5RlnFJMgq181Kn0nDhN5Iwy0FUEJ8/oqdS8fEz5mwQlHflX1 CLaquDVr/edr8LffvsFlxtSmeYNvZ2jYkSgroWeDhVR5Np1/LUCyh5y3edjVl/es B0/keuZ2fnYZnEfqLTpBEARYDBimymuu8gIoHK5nvtz3d/GGu92sVeda4LuHt8eH 1N+f41ceDR2JG/MIJbLr6PGYmCkAGSM/5Vcfa33G+A7GQT0EVb8jLozGCdrCjaEG OM33pN5wtv1M9gTLR9swITBWhbTpRWaHnXeZQF7ttaV8dvr/fuOzWBw47k8Jw0FJ zjGta66kwW7WkT3HDNoM2RRzm9dlJr1xdHOzAaVJnX3VHtHcIvYzDi90Xv9Nn46D E/qIpExmL4rMrb2+4MxT9CdbfzdBSmsnlRFoWZTIM1NPxA/97i7oAyYVAJ34LCNx xWqwimhXK14LzGffpSHm9CSz8DHNbehDZRMQD0jGYMn61PFtDB+E/oEq5AEqneuC KDht3Qdx/mPzJQPE8WV3d5FxeXfXDjj203x/i6x8TOdH8Bt4aoK9ajvPYBpA+2aE 4fPJIobLHGYN/F+GF1VJ =s9hz -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: Common Clock Framework rework Tegra already supports the common clock framework, but had issues: 1) The clock driver was located in arch/arm/mach-tegra/ rather than drivers/clk/. 2) A single "Tegra clock" type was implemented, rather than separate clock types for PLL, mux, divider, ... type in HW. 3) Clock lookups by device drivers were still driven by device name and connection ID, rather than through device tree. This pull request solves all three issues. This required some DT changes to add clocks properties, and driver changes to request clocks more "correctly". Finally, this rework allows all AUXDATA to be removed from Tegra board files, and various duplicate clock lookup entries to be removed from the driver. This pull request is based on the previous pull request, with tag tegra-for-3.9-cleanup. * tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (31 commits) clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s ARM: tegra30: remove auxdata ARM: tegra20: remove auxdata ASoC: tegra: remove auxdata staging: nvec: remove use of clk_get_sys ARM: tegra: paz00: add clock information to DT ARM: tegra: add clock properties to Tegra30 DT ARM: tegra: add clock properties to Tegra20 DT spi: tegra: do not use clock name to get clock ARM: tegra: remove legacy clock code ARM: tegra: migrate to new clock code clk: tegra: add clock support for Tegra30 clk: tegra: add clock support for Tegra20 clk: tegra: add Tegra specific clocks ARM: tegra: define Tegra30 CAR binding ARM: tegra: define Tegra20 CAR binding ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h ARM: tegra: add function to read chipid ARM: tegra: fix compile error when disable CPU_IDLE ... Signed-off-by: Olof Johansson <olof@lixom.net> Conflicts: arch/arm/mach-tegra/board-dt-tegra20.c arch/arm/mach-tegra/board-dt-tegra30.c arch/arm/mach-tegra/common.c arch/arm/mach-tegra/platsmp.c drivers/clocksource/Makefile
156 lines
3.7 KiB
C
156 lines
3.7 KiB
C
/*
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* nVidia Tegra device tree board support
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*
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* Copyright (C) 2010 Secret Lab Technologies, Ltd.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/pda_power.h>
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#include <linux/platform_data/tegra_usb.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c-tegra.h>
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#include <linux/usb/tegra_usb_phy.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/setup.h>
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#include "board.h"
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#include "common.h"
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#include "iomap.h"
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static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
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.operating_mode = TEGRA_USB_OTG,
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.power_down_on_bus_suspend = 1,
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.vbus_gpio = -1,
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};
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static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
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.reset_gpio = -1,
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.clk = "cdev2",
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};
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static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
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.phy_config = &tegra_ehci2_ulpi_phy_config,
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.operating_mode = TEGRA_USB_HOST,
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.power_down_on_bus_suspend = 1,
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.vbus_gpio = -1,
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};
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static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
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.operating_mode = TEGRA_USB_HOST,
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.power_down_on_bus_suspend = 1,
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.vbus_gpio = -1,
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};
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static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
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&tegra_ehci1_pdata),
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OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
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&tegra_ehci2_pdata),
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OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
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&tegra_ehci3_pdata),
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{}
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};
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static void __init tegra_dt_init(void)
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{
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/*
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* Finished with the static registrations now; fill in the missing
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* devices
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*/
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of_platform_populate(NULL, of_default_bus_match_table,
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tegra20_auxdata_lookup, NULL);
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}
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static void __init trimslice_init(void)
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{
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#ifdef CONFIG_TEGRA_PCI
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int ret;
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ret = tegra_pcie_init(true, true);
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if (ret)
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pr_err("tegra_pci_init() failed: %d\n", ret);
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#endif
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}
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static void __init harmony_init(void)
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{
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#ifdef CONFIG_TEGRA_PCI
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int ret;
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ret = harmony_pcie_init();
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if (ret)
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pr_err("harmony_pcie_init() failed: %d\n", ret);
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#endif
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}
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static void __init paz00_init(void)
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{
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tegra_paz00_wifikill_init();
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}
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static struct {
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char *machine;
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void (*init)(void);
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} board_init_funcs[] = {
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{ "compulab,trimslice", trimslice_init },
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{ "nvidia,harmony", harmony_init },
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{ "compal,paz00", paz00_init },
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};
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static void __init tegra_dt_init_late(void)
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{
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int i;
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tegra_init_late();
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for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
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if (of_machine_is_compatible(board_init_funcs[i].machine)) {
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board_init_funcs[i].init();
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break;
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}
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}
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}
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static const char *tegra20_dt_board_compat[] = {
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"nvidia,tegra20",
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NULL
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};
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DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
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.map_io = tegra_map_common_io,
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.smp = smp_ops(tegra_smp_ops),
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.init_early = tegra20_init_early,
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.init_irq = tegra_dt_init_irq,
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.init_time = clocksource_of_init,
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.init_machine = tegra_dt_init,
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.init_late = tegra_dt_init_late,
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.restart = tegra_assert_system_reset,
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.dt_compat = tegra20_dt_board_compat,
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MACHINE_END
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