Peter Ujfalusi b38434145b ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x ... McASP1 TX interrupt is 30, not 32 on DM646x DMSoC. While at it remove the bogus AEMIF interrupt entry from dm646x_default_priorities[]. AEMIF interrupt on DM6467 is 60 not 30 and the entry for the correct interrupt number is already present in the same table. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> [nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]] Signed-off-by: Sekhar Nori <nsekhar@ti.com>		2015-03-18 17:17:36 +05:30
..
mach	ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x	2015-03-18 17:17:36 +05:30