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e5447d2609
After updating to a more recent version of the Armada 375, we realized
that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ce3ed59dcd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
83 lines
4.1 KiB
Plaintext
83 lines
4.1 KiB
Plaintext
* Marvell Armada 375 SoC pinctrl driver for mpp
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Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "marvell,88f6720-pinctrl"
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- reg: register specifier of MPP registers
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Available mpp pins/groups and functions:
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Note: brackets (x) are not part of the mpp name for marvell,function and given
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only for more detailed description in this document.
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name pins functions
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================================================================================
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mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
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mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
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mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
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mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
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mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
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mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
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mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
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mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
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mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
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mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
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mpp10 10 gpio, dram(vttctrl), led(c1), nand(re)
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mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
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mpp12 12 gpio, dev(a1), audio(bclk)
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mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
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mpp14 14 gpio, i2c0(sda), uart1(txd)
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mpp15 15 gpio, i2c0(sck), uart1(rxd)
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mpp16 16 gpio, uart0(txd)
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mpp17 17 gpio, uart0(rxd)
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mpp18 18 gpio, tdm(intn)
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mpp19 19 gpio, tdm(rstn)
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mpp20 20 gpio, tdm(pclk)
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mpp21 21 gpio, tdm(fsync)
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mpp22 22 gpio, tdm(drx)
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mpp23 23 gpio, tdm(dtx)
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mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
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mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
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mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
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mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
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mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
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mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
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mpp30 30 gpio, ge1(txd0), spi1(cs0)
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mpp31 31 gpio, ge1(txd1), spi1(mosi)
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mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
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mpp33 33 gpio, ge1(txd3), spi1(miso)
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mpp34 34 gpio, ge1(txclkout), spi1(sck)
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mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
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mpp36 36 gpio, pcie0(clkreq)
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mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
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mpp38 38 gpio, pcie1(clkreq), ge(mdio)
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mpp39 39 gpio, ref(clkout)
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mpp40 40 gpio, uart1(txd)
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mpp41 41 gpio, uart1(rxd)
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mpp42 42 gpio, spi1(cs2), led(c0)
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mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
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mpp44 44 gpio, sata0(prsnt)
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mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
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mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
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mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
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mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
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mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
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mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
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mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
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mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
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mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
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mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
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mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
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mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
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mpp57 57 gpio, ge0(txctl), ge1(txctl)
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mpp58 58 gpio, led(c0)
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mpp59 59 gpio, led(c1)
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mpp60 60 gpio, uart1(txd), led(c2)
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mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
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mpp62 62 gpio, i2c1(sck), led(p1)
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mpp63 63 gpio, ptp(triggen), led(p2)
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mpp64 64 gpio, dram(vttctrl), led(p3)
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mpp65 65 gpio, sata1(prsnt)
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mpp66 66 gpio, ptp(eventreq), spi1(cs3)
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