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28389575a8
In commit0f987e25cb
, the source processing has been moved in front of the destination processing, but the error handling path has not been modified accordingly. Free resources in the correct order to avoid some leaks. Cc: <stable@vger.kernel.org> Fixes:0f987e25cb
("crypto: ixp4xx - Fix false lastlen uninitialised warning") Reported-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
1497 lines
36 KiB
C
1497 lines
36 KiB
C
/*
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* Intel IXP4xx NPE-C crypto driver
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*
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* Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/crypto.h>
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#include <linux/kernel.h>
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#include <linux/rtnetlink.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/gfp.h>
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#include <linux/module.h>
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#include <crypto/ctr.h>
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#include <crypto/des.h>
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#include <crypto/aes.h>
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#include <crypto/hmac.h>
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#include <crypto/sha.h>
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#include <crypto/algapi.h>
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#include <crypto/internal/aead.h>
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#include <crypto/authenc.h>
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#include <crypto/scatterwalk.h>
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#include <mach/npe.h>
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#include <mach/qmgr.h>
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#define MAX_KEYLEN 32
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/* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
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#define NPE_CTX_LEN 80
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#define AES_BLOCK128 16
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#define NPE_OP_HASH_VERIFY 0x01
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#define NPE_OP_CCM_ENABLE 0x04
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#define NPE_OP_CRYPT_ENABLE 0x08
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#define NPE_OP_HASH_ENABLE 0x10
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#define NPE_OP_NOT_IN_PLACE 0x20
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#define NPE_OP_HMAC_DISABLE 0x40
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#define NPE_OP_CRYPT_ENCRYPT 0x80
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#define NPE_OP_CCM_GEN_MIC 0xcc
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#define NPE_OP_HASH_GEN_ICV 0x50
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#define NPE_OP_ENC_GEN_KEY 0xc9
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#define MOD_ECB 0x0000
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#define MOD_CTR 0x1000
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#define MOD_CBC_ENC 0x2000
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#define MOD_CBC_DEC 0x3000
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#define MOD_CCM_ENC 0x4000
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#define MOD_CCM_DEC 0x5000
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#define KEYLEN_128 4
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#define KEYLEN_192 6
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#define KEYLEN_256 8
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#define CIPH_DECR 0x0000
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#define CIPH_ENCR 0x0400
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#define MOD_DES 0x0000
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#define MOD_TDEA2 0x0100
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#define MOD_3DES 0x0200
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#define MOD_AES 0x0800
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#define MOD_AES128 (0x0800 | KEYLEN_128)
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#define MOD_AES192 (0x0900 | KEYLEN_192)
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#define MOD_AES256 (0x0a00 | KEYLEN_256)
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#define MAX_IVLEN 16
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#define NPE_ID 2 /* NPE C */
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#define NPE_QLEN 16
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/* Space for registering when the first
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* NPE_QLEN crypt_ctl are busy */
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#define NPE_QLEN_TOTAL 64
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#define SEND_QID 29
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#define RECV_QID 30
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#define CTL_FLAG_UNUSED 0x0000
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#define CTL_FLAG_USED 0x1000
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#define CTL_FLAG_PERFORM_ABLK 0x0001
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#define CTL_FLAG_GEN_ICV 0x0002
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#define CTL_FLAG_GEN_REVAES 0x0004
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#define CTL_FLAG_PERFORM_AEAD 0x0008
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#define CTL_FLAG_MASK 0x000f
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#define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
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#define MD5_DIGEST_SIZE 16
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struct buffer_desc {
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u32 phys_next;
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#ifdef __ARMEB__
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u16 buf_len;
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u16 pkt_len;
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#else
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u16 pkt_len;
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u16 buf_len;
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#endif
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u32 phys_addr;
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u32 __reserved[4];
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struct buffer_desc *next;
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enum dma_data_direction dir;
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};
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struct crypt_ctl {
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#ifdef __ARMEB__
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u8 mode; /* NPE_OP_* operation mode */
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u8 init_len;
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u16 reserved;
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#else
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u16 reserved;
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u8 init_len;
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u8 mode; /* NPE_OP_* operation mode */
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#endif
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u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
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u32 icv_rev_aes; /* icv or rev aes */
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u32 src_buf;
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u32 dst_buf;
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#ifdef __ARMEB__
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u16 auth_offs; /* Authentication start offset */
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u16 auth_len; /* Authentication data length */
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u16 crypt_offs; /* Cryption start offset */
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u16 crypt_len; /* Cryption data length */
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#else
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u16 auth_len; /* Authentication data length */
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u16 auth_offs; /* Authentication start offset */
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u16 crypt_len; /* Cryption data length */
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u16 crypt_offs; /* Cryption start offset */
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#endif
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u32 aadAddr; /* Additional Auth Data Addr for CCM mode */
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u32 crypto_ctx; /* NPE Crypto Param structure address */
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/* Used by Host: 4*4 bytes*/
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unsigned ctl_flags;
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union {
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struct ablkcipher_request *ablk_req;
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struct aead_request *aead_req;
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struct crypto_tfm *tfm;
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} data;
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struct buffer_desc *regist_buf;
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u8 *regist_ptr;
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};
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struct ablk_ctx {
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struct buffer_desc *src;
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struct buffer_desc *dst;
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};
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struct aead_ctx {
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struct buffer_desc *src;
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struct buffer_desc *dst;
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struct scatterlist ivlist;
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/* used when the hmac is not on one sg entry */
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u8 *hmac_virt;
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int encrypt;
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};
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struct ix_hash_algo {
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u32 cfgword;
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unsigned char *icv;
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};
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struct ix_sa_dir {
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unsigned char *npe_ctx;
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dma_addr_t npe_ctx_phys;
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int npe_ctx_idx;
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u8 npe_mode;
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};
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struct ixp_ctx {
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struct ix_sa_dir encrypt;
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struct ix_sa_dir decrypt;
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int authkey_len;
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u8 authkey[MAX_KEYLEN];
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int enckey_len;
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u8 enckey[MAX_KEYLEN];
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u8 salt[MAX_IVLEN];
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u8 nonce[CTR_RFC3686_NONCE_SIZE];
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unsigned salted;
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atomic_t configuring;
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struct completion completion;
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};
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struct ixp_alg {
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struct crypto_alg crypto;
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const struct ix_hash_algo *hash;
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u32 cfg_enc;
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u32 cfg_dec;
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int registered;
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};
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struct ixp_aead_alg {
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struct aead_alg crypto;
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const struct ix_hash_algo *hash;
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u32 cfg_enc;
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u32 cfg_dec;
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int registered;
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};
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static const struct ix_hash_algo hash_alg_md5 = {
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.cfgword = 0xAA010004,
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.icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
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"\xFE\xDC\xBA\x98\x76\x54\x32\x10",
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};
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static const struct ix_hash_algo hash_alg_sha1 = {
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.cfgword = 0x00000005,
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.icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
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"\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
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};
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static struct npe *npe_c;
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static struct dma_pool *buffer_pool = NULL;
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static struct dma_pool *ctx_pool = NULL;
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static struct crypt_ctl *crypt_virt = NULL;
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static dma_addr_t crypt_phys;
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static int support_aes = 1;
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#define DRIVER_NAME "ixp4xx_crypto"
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static struct platform_device *pdev;
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static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
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{
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return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
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}
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static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
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{
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return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
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}
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static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
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{
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return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
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}
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static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
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{
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return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
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}
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static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
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{
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return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
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}
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static int setup_crypt_desc(void)
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{
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struct device *dev = &pdev->dev;
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BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
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crypt_virt = dma_alloc_coherent(dev,
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NPE_QLEN * sizeof(struct crypt_ctl),
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&crypt_phys, GFP_ATOMIC);
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if (!crypt_virt)
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return -ENOMEM;
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memset(crypt_virt, 0, NPE_QLEN * sizeof(struct crypt_ctl));
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return 0;
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}
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static spinlock_t desc_lock;
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static struct crypt_ctl *get_crypt_desc(void)
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{
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int i;
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static int idx = 0;
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unsigned long flags;
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spin_lock_irqsave(&desc_lock, flags);
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if (unlikely(!crypt_virt))
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setup_crypt_desc();
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if (unlikely(!crypt_virt)) {
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spin_unlock_irqrestore(&desc_lock, flags);
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return NULL;
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}
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i = idx;
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if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
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if (++idx >= NPE_QLEN)
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idx = 0;
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crypt_virt[i].ctl_flags = CTL_FLAG_USED;
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spin_unlock_irqrestore(&desc_lock, flags);
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return crypt_virt +i;
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} else {
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spin_unlock_irqrestore(&desc_lock, flags);
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return NULL;
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}
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}
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static spinlock_t emerg_lock;
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static struct crypt_ctl *get_crypt_desc_emerg(void)
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{
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int i;
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static int idx = NPE_QLEN;
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struct crypt_ctl *desc;
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unsigned long flags;
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desc = get_crypt_desc();
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if (desc)
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return desc;
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if (unlikely(!crypt_virt))
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return NULL;
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spin_lock_irqsave(&emerg_lock, flags);
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i = idx;
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if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
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if (++idx >= NPE_QLEN_TOTAL)
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idx = NPE_QLEN;
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crypt_virt[i].ctl_flags = CTL_FLAG_USED;
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spin_unlock_irqrestore(&emerg_lock, flags);
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return crypt_virt +i;
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} else {
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spin_unlock_irqrestore(&emerg_lock, flags);
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return NULL;
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}
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}
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static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
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{
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while (buf) {
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struct buffer_desc *buf1;
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u32 phys1;
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buf1 = buf->next;
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phys1 = buf->phys_next;
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dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
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dma_pool_free(buffer_pool, buf, phys);
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buf = buf1;
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phys = phys1;
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}
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}
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static struct tasklet_struct crypto_done_tasklet;
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static void finish_scattered_hmac(struct crypt_ctl *crypt)
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{
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struct aead_request *req = crypt->data.aead_req;
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struct aead_ctx *req_ctx = aead_request_ctx(req);
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struct crypto_aead *tfm = crypto_aead_reqtfm(req);
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int authsize = crypto_aead_authsize(tfm);
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int decryptlen = req->assoclen + req->cryptlen - authsize;
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if (req_ctx->encrypt) {
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scatterwalk_map_and_copy(req_ctx->hmac_virt,
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req->dst, decryptlen, authsize, 1);
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}
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dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
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}
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static void one_packet(dma_addr_t phys)
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{
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struct device *dev = &pdev->dev;
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struct crypt_ctl *crypt;
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struct ixp_ctx *ctx;
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int failed;
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failed = phys & 0x1 ? -EBADMSG : 0;
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phys &= ~0x3;
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crypt = crypt_phys2virt(phys);
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switch (crypt->ctl_flags & CTL_FLAG_MASK) {
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case CTL_FLAG_PERFORM_AEAD: {
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struct aead_request *req = crypt->data.aead_req;
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struct aead_ctx *req_ctx = aead_request_ctx(req);
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free_buf_chain(dev, req_ctx->src, crypt->src_buf);
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free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
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if (req_ctx->hmac_virt) {
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finish_scattered_hmac(crypt);
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}
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req->base.complete(&req->base, failed);
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break;
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}
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case CTL_FLAG_PERFORM_ABLK: {
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struct ablkcipher_request *req = crypt->data.ablk_req;
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struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
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if (req_ctx->dst) {
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free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
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}
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free_buf_chain(dev, req_ctx->src, crypt->src_buf);
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req->base.complete(&req->base, failed);
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break;
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}
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case CTL_FLAG_GEN_ICV:
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ctx = crypto_tfm_ctx(crypt->data.tfm);
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dma_pool_free(ctx_pool, crypt->regist_ptr,
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crypt->regist_buf->phys_addr);
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dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
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if (atomic_dec_and_test(&ctx->configuring))
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complete(&ctx->completion);
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break;
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case CTL_FLAG_GEN_REVAES:
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ctx = crypto_tfm_ctx(crypt->data.tfm);
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*(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
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if (atomic_dec_and_test(&ctx->configuring))
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complete(&ctx->completion);
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break;
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default:
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BUG();
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}
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crypt->ctl_flags = CTL_FLAG_UNUSED;
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}
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static void irqhandler(void *_unused)
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{
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tasklet_schedule(&crypto_done_tasklet);
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}
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static void crypto_done_action(unsigned long arg)
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{
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int i;
|
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for(i=0; i<4; i++) {
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dma_addr_t phys = qmgr_get_entry(RECV_QID);
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if (!phys)
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return;
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one_packet(phys);
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}
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tasklet_schedule(&crypto_done_tasklet);
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}
|
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|
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static int init_ixp_crypto(struct device *dev)
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{
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int ret = -ENODEV;
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u32 msg[2] = { 0, 0 };
|
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|
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if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
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IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
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printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
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return ret;
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}
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npe_c = npe_request(NPE_ID);
|
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if (!npe_c)
|
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return ret;
|
|
|
|
if (!npe_running(npe_c)) {
|
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ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
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if (ret)
|
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goto npe_release;
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if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
|
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goto npe_error;
|
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} else {
|
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if (npe_send_message(npe_c, msg, "STATUS_MSG"))
|
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goto npe_error;
|
|
|
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if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
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goto npe_error;
|
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}
|
|
|
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switch ((msg[1]>>16) & 0xff) {
|
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case 3:
|
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printk(KERN_WARNING "Firmware of %s lacks AES support\n",
|
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npe_name(npe_c));
|
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support_aes = 0;
|
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break;
|
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case 4:
|
|
case 5:
|
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support_aes = 1;
|
|
break;
|
|
default:
|
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printk(KERN_ERR "Firmware of %s lacks crypto support\n",
|
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npe_name(npe_c));
|
|
ret = -ENODEV;
|
|
goto npe_release;
|
|
}
|
|
/* buffer_pool will also be used to sometimes store the hmac,
|
|
* so assure it is large enough
|
|
*/
|
|
BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
|
|
buffer_pool = dma_pool_create("buffer", dev,
|
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sizeof(struct buffer_desc), 32, 0);
|
|
ret = -ENOMEM;
|
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if (!buffer_pool) {
|
|
goto err;
|
|
}
|
|
ctx_pool = dma_pool_create("context", dev,
|
|
NPE_CTX_LEN, 16, 0);
|
|
if (!ctx_pool) {
|
|
goto err;
|
|
}
|
|
ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
|
|
"ixp_crypto:out", NULL);
|
|
if (ret)
|
|
goto err;
|
|
ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
|
|
"ixp_crypto:in", NULL);
|
|
if (ret) {
|
|
qmgr_release_queue(SEND_QID);
|
|
goto err;
|
|
}
|
|
qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
|
|
tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
|
|
|
|
qmgr_enable_irq(RECV_QID);
|
|
return 0;
|
|
|
|
npe_error:
|
|
printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
|
|
ret = -EIO;
|
|
err:
|
|
dma_pool_destroy(ctx_pool);
|
|
dma_pool_destroy(buffer_pool);
|
|
npe_release:
|
|
npe_release(npe_c);
|
|
return ret;
|
|
}
|
|
|
|
static void release_ixp_crypto(struct device *dev)
|
|
{
|
|
qmgr_disable_irq(RECV_QID);
|
|
tasklet_kill(&crypto_done_tasklet);
|
|
|
|
qmgr_release_queue(SEND_QID);
|
|
qmgr_release_queue(RECV_QID);
|
|
|
|
dma_pool_destroy(ctx_pool);
|
|
dma_pool_destroy(buffer_pool);
|
|
|
|
npe_release(npe_c);
|
|
|
|
if (crypt_virt) {
|
|
dma_free_coherent(dev,
|
|
NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
|
|
crypt_virt, crypt_phys);
|
|
}
|
|
return;
|
|
}
|
|
|
|
static void reset_sa_dir(struct ix_sa_dir *dir)
|
|
{
|
|
memset(dir->npe_ctx, 0, NPE_CTX_LEN);
|
|
dir->npe_ctx_idx = 0;
|
|
dir->npe_mode = 0;
|
|
}
|
|
|
|
static int init_sa_dir(struct ix_sa_dir *dir)
|
|
{
|
|
dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
|
|
if (!dir->npe_ctx) {
|
|
return -ENOMEM;
|
|
}
|
|
reset_sa_dir(dir);
|
|
return 0;
|
|
}
|
|
|
|
static void free_sa_dir(struct ix_sa_dir *dir)
|
|
{
|
|
memset(dir->npe_ctx, 0, NPE_CTX_LEN);
|
|
dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
|
|
}
|
|
|
|
static int init_tfm(struct crypto_tfm *tfm)
|
|
{
|
|
struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
int ret;
|
|
|
|
atomic_set(&ctx->configuring, 0);
|
|
ret = init_sa_dir(&ctx->encrypt);
|
|
if (ret)
|
|
return ret;
|
|
ret = init_sa_dir(&ctx->decrypt);
|
|
if (ret) {
|
|
free_sa_dir(&ctx->encrypt);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int init_tfm_ablk(struct crypto_tfm *tfm)
|
|
{
|
|
tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
|
|
return init_tfm(tfm);
|
|
}
|
|
|
|
static int init_tfm_aead(struct crypto_aead *tfm)
|
|
{
|
|
crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx));
|
|
return init_tfm(crypto_aead_tfm(tfm));
|
|
}
|
|
|
|
static void exit_tfm(struct crypto_tfm *tfm)
|
|
{
|
|
struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
free_sa_dir(&ctx->encrypt);
|
|
free_sa_dir(&ctx->decrypt);
|
|
}
|
|
|
|
static void exit_tfm_aead(struct crypto_aead *tfm)
|
|
{
|
|
exit_tfm(crypto_aead_tfm(tfm));
|
|
}
|
|
|
|
static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
|
|
int init_len, u32 ctx_addr, const u8 *key, int key_len)
|
|
{
|
|
struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct crypt_ctl *crypt;
|
|
struct buffer_desc *buf;
|
|
int i;
|
|
u8 *pad;
|
|
u32 pad_phys, buf_phys;
|
|
|
|
BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
|
|
pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
|
|
if (!pad)
|
|
return -ENOMEM;
|
|
buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
|
|
if (!buf) {
|
|
dma_pool_free(ctx_pool, pad, pad_phys);
|
|
return -ENOMEM;
|
|
}
|
|
crypt = get_crypt_desc_emerg();
|
|
if (!crypt) {
|
|
dma_pool_free(ctx_pool, pad, pad_phys);
|
|
dma_pool_free(buffer_pool, buf, buf_phys);
|
|
return -EAGAIN;
|
|
}
|
|
|
|
memcpy(pad, key, key_len);
|
|
memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
|
|
for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
|
|
pad[i] ^= xpad;
|
|
}
|
|
|
|
crypt->data.tfm = tfm;
|
|
crypt->regist_ptr = pad;
|
|
crypt->regist_buf = buf;
|
|
|
|
crypt->auth_offs = 0;
|
|
crypt->auth_len = HMAC_PAD_BLOCKLEN;
|
|
crypt->crypto_ctx = ctx_addr;
|
|
crypt->src_buf = buf_phys;
|
|
crypt->icv_rev_aes = target;
|
|
crypt->mode = NPE_OP_HASH_GEN_ICV;
|
|
crypt->init_len = init_len;
|
|
crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
|
|
|
|
buf->next = 0;
|
|
buf->buf_len = HMAC_PAD_BLOCKLEN;
|
|
buf->pkt_len = 0;
|
|
buf->phys_addr = pad_phys;
|
|
|
|
atomic_inc(&ctx->configuring);
|
|
qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
|
|
BUG_ON(qmgr_stat_overflow(SEND_QID));
|
|
return 0;
|
|
}
|
|
|
|
static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
|
|
const u8 *key, int key_len, unsigned digest_len)
|
|
{
|
|
u32 itarget, otarget, npe_ctx_addr;
|
|
unsigned char *cinfo;
|
|
int init_len, ret = 0;
|
|
u32 cfgword;
|
|
struct ix_sa_dir *dir;
|
|
struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
const struct ix_hash_algo *algo;
|
|
|
|
dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
|
|
cinfo = dir->npe_ctx + dir->npe_ctx_idx;
|
|
algo = ix_hash(tfm);
|
|
|
|
/* write cfg word to cryptinfo */
|
|
cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
|
|
#ifndef __ARMEB__
|
|
cfgword ^= 0xAA000000; /* change the "byte swap" flags */
|
|
#endif
|
|
*(u32*)cinfo = cpu_to_be32(cfgword);
|
|
cinfo += sizeof(cfgword);
|
|
|
|
/* write ICV to cryptinfo */
|
|
memcpy(cinfo, algo->icv, digest_len);
|
|
cinfo += digest_len;
|
|
|
|
itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
|
|
+ sizeof(algo->cfgword);
|
|
otarget = itarget + digest_len;
|
|
init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
|
|
npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
|
|
|
|
dir->npe_ctx_idx += init_len;
|
|
dir->npe_mode |= NPE_OP_HASH_ENABLE;
|
|
|
|
if (!encrypt)
|
|
dir->npe_mode |= NPE_OP_HASH_VERIFY;
|
|
|
|
ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
|
|
init_len, npe_ctx_addr, key, key_len);
|
|
if (ret)
|
|
return ret;
|
|
return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
|
|
init_len, npe_ctx_addr, key, key_len);
|
|
}
|
|
|
|
static int gen_rev_aes_key(struct crypto_tfm *tfm)
|
|
{
|
|
struct crypt_ctl *crypt;
|
|
struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct ix_sa_dir *dir = &ctx->decrypt;
|
|
|
|
crypt = get_crypt_desc_emerg();
|
|
if (!crypt) {
|
|
return -EAGAIN;
|
|
}
|
|
*(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
|
|
|
|
crypt->data.tfm = tfm;
|
|
crypt->crypt_offs = 0;
|
|
crypt->crypt_len = AES_BLOCK128;
|
|
crypt->src_buf = 0;
|
|
crypt->crypto_ctx = dir->npe_ctx_phys;
|
|
crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
|
|
crypt->mode = NPE_OP_ENC_GEN_KEY;
|
|
crypt->init_len = dir->npe_ctx_idx;
|
|
crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
|
|
|
|
atomic_inc(&ctx->configuring);
|
|
qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
|
|
BUG_ON(qmgr_stat_overflow(SEND_QID));
|
|
return 0;
|
|
}
|
|
|
|
static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
|
|
const u8 *key, int key_len)
|
|
{
|
|
u8 *cinfo;
|
|
u32 cipher_cfg;
|
|
u32 keylen_cfg = 0;
|
|
struct ix_sa_dir *dir;
|
|
struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
u32 *flags = &tfm->crt_flags;
|
|
|
|
dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
|
|
cinfo = dir->npe_ctx;
|
|
|
|
if (encrypt) {
|
|
cipher_cfg = cipher_cfg_enc(tfm);
|
|
dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
|
|
} else {
|
|
cipher_cfg = cipher_cfg_dec(tfm);
|
|
}
|
|
if (cipher_cfg & MOD_AES) {
|
|
switch (key_len) {
|
|
case 16: keylen_cfg = MOD_AES128; break;
|
|
case 24: keylen_cfg = MOD_AES192; break;
|
|
case 32: keylen_cfg = MOD_AES256; break;
|
|
default:
|
|
*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
|
|
return -EINVAL;
|
|
}
|
|
cipher_cfg |= keylen_cfg;
|
|
} else if (cipher_cfg & MOD_3DES) {
|
|
const u32 *K = (const u32 *)key;
|
|
if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) ||
|
|
!((K[2] ^ K[4]) | (K[3] ^ K[5]))))
|
|
{
|
|
*flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
|
|
return -EINVAL;
|
|
}
|
|
} else {
|
|
u32 tmp[DES_EXPKEY_WORDS];
|
|
if (des_ekey(tmp, key) == 0) {
|
|
*flags |= CRYPTO_TFM_RES_WEAK_KEY;
|
|
}
|
|
}
|
|
/* write cfg word to cryptinfo */
|
|
*(u32*)cinfo = cpu_to_be32(cipher_cfg);
|
|
cinfo += sizeof(cipher_cfg);
|
|
|
|
/* write cipher key to cryptinfo */
|
|
memcpy(cinfo, key, key_len);
|
|
/* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
|
|
if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
|
|
memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
|
|
key_len = DES3_EDE_KEY_SIZE;
|
|
}
|
|
dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
|
|
dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
|
|
if ((cipher_cfg & MOD_AES) && !encrypt) {
|
|
return gen_rev_aes_key(tfm);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct buffer_desc *chainup_buffers(struct device *dev,
|
|
struct scatterlist *sg, unsigned nbytes,
|
|
struct buffer_desc *buf, gfp_t flags,
|
|
enum dma_data_direction dir)
|
|
{
|
|
for (; nbytes > 0; sg = sg_next(sg)) {
|
|
unsigned len = min(nbytes, sg->length);
|
|
struct buffer_desc *next_buf;
|
|
u32 next_buf_phys;
|
|
void *ptr;
|
|
|
|
nbytes -= len;
|
|
ptr = sg_virt(sg);
|
|
next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
|
|
if (!next_buf) {
|
|
buf = NULL;
|
|
break;
|
|
}
|
|
sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
|
|
buf->next = next_buf;
|
|
buf->phys_next = next_buf_phys;
|
|
buf = next_buf;
|
|
|
|
buf->phys_addr = sg_dma_address(sg);
|
|
buf->buf_len = len;
|
|
buf->dir = dir;
|
|
}
|
|
buf->next = NULL;
|
|
buf->phys_next = 0;
|
|
return buf;
|
|
}
|
|
|
|
static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
|
|
unsigned int key_len)
|
|
{
|
|
struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
|
|
u32 *flags = &tfm->base.crt_flags;
|
|
int ret;
|
|
|
|
init_completion(&ctx->completion);
|
|
atomic_inc(&ctx->configuring);
|
|
|
|
reset_sa_dir(&ctx->encrypt);
|
|
reset_sa_dir(&ctx->decrypt);
|
|
|
|
ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
|
|
ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
|
|
|
|
ret = setup_cipher(&tfm->base, 0, key, key_len);
|
|
if (ret)
|
|
goto out;
|
|
ret = setup_cipher(&tfm->base, 1, key, key_len);
|
|
if (ret)
|
|
goto out;
|
|
|
|
if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
|
|
if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
|
|
ret = -EINVAL;
|
|
} else {
|
|
*flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
|
|
}
|
|
}
|
|
out:
|
|
if (!atomic_dec_and_test(&ctx->configuring))
|
|
wait_for_completion(&ctx->completion);
|
|
return ret;
|
|
}
|
|
|
|
static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
|
|
unsigned int key_len)
|
|
{
|
|
struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
|
|
|
|
/* the nonce is stored in bytes at end of key */
|
|
if (key_len < CTR_RFC3686_NONCE_SIZE)
|
|
return -EINVAL;
|
|
|
|
memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
|
|
CTR_RFC3686_NONCE_SIZE);
|
|
|
|
key_len -= CTR_RFC3686_NONCE_SIZE;
|
|
return ablk_setkey(tfm, key, key_len);
|
|
}
|
|
|
|
static int ablk_perform(struct ablkcipher_request *req, int encrypt)
|
|
{
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
|
struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
|
|
unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
|
|
struct ix_sa_dir *dir;
|
|
struct crypt_ctl *crypt;
|
|
unsigned int nbytes = req->nbytes;
|
|
enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
|
|
struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
|
|
struct buffer_desc src_hook;
|
|
struct device *dev = &pdev->dev;
|
|
gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
|
|
GFP_KERNEL : GFP_ATOMIC;
|
|
|
|
if (qmgr_stat_full(SEND_QID))
|
|
return -EAGAIN;
|
|
if (atomic_read(&ctx->configuring))
|
|
return -EAGAIN;
|
|
|
|
dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
|
|
|
|
crypt = get_crypt_desc();
|
|
if (!crypt)
|
|
return -ENOMEM;
|
|
|
|
crypt->data.ablk_req = req;
|
|
crypt->crypto_ctx = dir->npe_ctx_phys;
|
|
crypt->mode = dir->npe_mode;
|
|
crypt->init_len = dir->npe_ctx_idx;
|
|
|
|
crypt->crypt_offs = 0;
|
|
crypt->crypt_len = nbytes;
|
|
|
|
BUG_ON(ivsize && !req->info);
|
|
memcpy(crypt->iv, req->info, ivsize);
|
|
if (req->src != req->dst) {
|
|
struct buffer_desc dst_hook;
|
|
crypt->mode |= NPE_OP_NOT_IN_PLACE;
|
|
/* This was never tested by Intel
|
|
* for more than one dst buffer, I think. */
|
|
req_ctx->dst = NULL;
|
|
if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
|
|
flags, DMA_FROM_DEVICE))
|
|
goto free_buf_dest;
|
|
src_direction = DMA_TO_DEVICE;
|
|
req_ctx->dst = dst_hook.next;
|
|
crypt->dst_buf = dst_hook.phys_next;
|
|
} else {
|
|
req_ctx->dst = NULL;
|
|
}
|
|
req_ctx->src = NULL;
|
|
if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
|
|
flags, src_direction))
|
|
goto free_buf_src;
|
|
|
|
req_ctx->src = src_hook.next;
|
|
crypt->src_buf = src_hook.phys_next;
|
|
crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
|
|
qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
|
|
BUG_ON(qmgr_stat_overflow(SEND_QID));
|
|
return -EINPROGRESS;
|
|
|
|
free_buf_src:
|
|
free_buf_chain(dev, req_ctx->src, crypt->src_buf);
|
|
free_buf_dest:
|
|
if (req->src != req->dst) {
|
|
free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
|
|
}
|
|
crypt->ctl_flags = CTL_FLAG_UNUSED;
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static int ablk_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return ablk_perform(req, 1);
|
|
}
|
|
|
|
static int ablk_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return ablk_perform(req, 0);
|
|
}
|
|
|
|
static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
|
|
{
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
|
struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
|
|
u8 iv[CTR_RFC3686_BLOCK_SIZE];
|
|
u8 *info = req->info;
|
|
int ret;
|
|
|
|
/* set up counter block */
|
|
memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
|
|
memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
|
|
|
|
/* initialize counter portion of counter block */
|
|
*(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
|
|
cpu_to_be32(1);
|
|
|
|
req->info = iv;
|
|
ret = ablk_perform(req, 1);
|
|
req->info = info;
|
|
return ret;
|
|
}
|
|
|
|
static int aead_perform(struct aead_request *req, int encrypt,
|
|
int cryptoffset, int eff_cryptlen, u8 *iv)
|
|
{
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
|
|
unsigned ivsize = crypto_aead_ivsize(tfm);
|
|
unsigned authsize = crypto_aead_authsize(tfm);
|
|
struct ix_sa_dir *dir;
|
|
struct crypt_ctl *crypt;
|
|
unsigned int cryptlen;
|
|
struct buffer_desc *buf, src_hook;
|
|
struct aead_ctx *req_ctx = aead_request_ctx(req);
|
|
struct device *dev = &pdev->dev;
|
|
gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
|
|
GFP_KERNEL : GFP_ATOMIC;
|
|
enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
|
|
unsigned int lastlen;
|
|
|
|
if (qmgr_stat_full(SEND_QID))
|
|
return -EAGAIN;
|
|
if (atomic_read(&ctx->configuring))
|
|
return -EAGAIN;
|
|
|
|
if (encrypt) {
|
|
dir = &ctx->encrypt;
|
|
cryptlen = req->cryptlen;
|
|
} else {
|
|
dir = &ctx->decrypt;
|
|
/* req->cryptlen includes the authsize when decrypting */
|
|
cryptlen = req->cryptlen -authsize;
|
|
eff_cryptlen -= authsize;
|
|
}
|
|
crypt = get_crypt_desc();
|
|
if (!crypt)
|
|
return -ENOMEM;
|
|
|
|
crypt->data.aead_req = req;
|
|
crypt->crypto_ctx = dir->npe_ctx_phys;
|
|
crypt->mode = dir->npe_mode;
|
|
crypt->init_len = dir->npe_ctx_idx;
|
|
|
|
crypt->crypt_offs = cryptoffset;
|
|
crypt->crypt_len = eff_cryptlen;
|
|
|
|
crypt->auth_offs = 0;
|
|
crypt->auth_len = req->assoclen + cryptlen;
|
|
BUG_ON(ivsize && !req->iv);
|
|
memcpy(crypt->iv, req->iv, ivsize);
|
|
|
|
buf = chainup_buffers(dev, req->src, crypt->auth_len,
|
|
&src_hook, flags, src_direction);
|
|
req_ctx->src = src_hook.next;
|
|
crypt->src_buf = src_hook.phys_next;
|
|
if (!buf)
|
|
goto free_buf_src;
|
|
|
|
lastlen = buf->buf_len;
|
|
if (lastlen >= authsize)
|
|
crypt->icv_rev_aes = buf->phys_addr +
|
|
buf->buf_len - authsize;
|
|
|
|
req_ctx->dst = NULL;
|
|
|
|
if (req->src != req->dst) {
|
|
struct buffer_desc dst_hook;
|
|
|
|
crypt->mode |= NPE_OP_NOT_IN_PLACE;
|
|
src_direction = DMA_TO_DEVICE;
|
|
|
|
buf = chainup_buffers(dev, req->dst, crypt->auth_len,
|
|
&dst_hook, flags, DMA_FROM_DEVICE);
|
|
req_ctx->dst = dst_hook.next;
|
|
crypt->dst_buf = dst_hook.phys_next;
|
|
|
|
if (!buf)
|
|
goto free_buf_dst;
|
|
|
|
if (encrypt) {
|
|
lastlen = buf->buf_len;
|
|
if (lastlen >= authsize)
|
|
crypt->icv_rev_aes = buf->phys_addr +
|
|
buf->buf_len - authsize;
|
|
}
|
|
}
|
|
|
|
if (unlikely(lastlen < authsize)) {
|
|
/* The 12 hmac bytes are scattered,
|
|
* we need to copy them into a safe buffer */
|
|
req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
|
|
&crypt->icv_rev_aes);
|
|
if (unlikely(!req_ctx->hmac_virt))
|
|
goto free_buf_dst;
|
|
if (!encrypt) {
|
|
scatterwalk_map_and_copy(req_ctx->hmac_virt,
|
|
req->src, cryptlen, authsize, 0);
|
|
}
|
|
req_ctx->encrypt = encrypt;
|
|
} else {
|
|
req_ctx->hmac_virt = NULL;
|
|
}
|
|
|
|
crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
|
|
qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
|
|
BUG_ON(qmgr_stat_overflow(SEND_QID));
|
|
return -EINPROGRESS;
|
|
|
|
free_buf_dst:
|
|
free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
|
|
free_buf_src:
|
|
free_buf_chain(dev, req_ctx->src, crypt->src_buf);
|
|
crypt->ctl_flags = CTL_FLAG_UNUSED;
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
|
|
{
|
|
struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
|
|
u32 *flags = &tfm->base.crt_flags;
|
|
unsigned digest_len = crypto_aead_maxauthsize(tfm);
|
|
int ret;
|
|
|
|
if (!ctx->enckey_len && !ctx->authkey_len)
|
|
return 0;
|
|
init_completion(&ctx->completion);
|
|
atomic_inc(&ctx->configuring);
|
|
|
|
reset_sa_dir(&ctx->encrypt);
|
|
reset_sa_dir(&ctx->decrypt);
|
|
|
|
ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
|
|
if (ret)
|
|
goto out;
|
|
ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
|
|
if (ret)
|
|
goto out;
|
|
ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
|
|
ctx->authkey_len, digest_len);
|
|
if (ret)
|
|
goto out;
|
|
ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey,
|
|
ctx->authkey_len, digest_len);
|
|
if (ret)
|
|
goto out;
|
|
|
|
if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
|
|
if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
} else {
|
|
*flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
|
|
}
|
|
}
|
|
out:
|
|
if (!atomic_dec_and_test(&ctx->configuring))
|
|
wait_for_completion(&ctx->completion);
|
|
return ret;
|
|
}
|
|
|
|
static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
|
|
{
|
|
int max = crypto_aead_maxauthsize(tfm) >> 2;
|
|
|
|
if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
|
|
return -EINVAL;
|
|
return aead_setup(tfm, authsize);
|
|
}
|
|
|
|
static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
|
|
unsigned int keylen)
|
|
{
|
|
struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
|
|
struct crypto_authenc_keys keys;
|
|
|
|
if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
|
|
goto badkey;
|
|
|
|
if (keys.authkeylen > sizeof(ctx->authkey))
|
|
goto badkey;
|
|
|
|
if (keys.enckeylen > sizeof(ctx->enckey))
|
|
goto badkey;
|
|
|
|
memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
|
|
memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
|
|
ctx->authkey_len = keys.authkeylen;
|
|
ctx->enckey_len = keys.enckeylen;
|
|
|
|
return aead_setup(tfm, crypto_aead_authsize(tfm));
|
|
badkey:
|
|
crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int aead_encrypt(struct aead_request *req)
|
|
{
|
|
return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv);
|
|
}
|
|
|
|
static int aead_decrypt(struct aead_request *req)
|
|
{
|
|
return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv);
|
|
}
|
|
|
|
static struct ixp_alg ixp4xx_algos[] = {
|
|
{
|
|
.crypto = {
|
|
.cra_name = "cbc(des)",
|
|
.cra_blocksize = DES_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.geniv = "eseqiv",
|
|
}
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
|
|
|
|
}, {
|
|
.crypto = {
|
|
.cra_name = "ecb(des)",
|
|
.cra_blocksize = DES_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
}
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
|
|
}, {
|
|
.crypto = {
|
|
.cra_name = "cbc(des3_ede)",
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
.geniv = "eseqiv",
|
|
}
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
|
|
}, {
|
|
.crypto = {
|
|
.cra_name = "ecb(des3_ede)",
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
}
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
|
|
}, {
|
|
.crypto = {
|
|
.cra_name = "cbc(aes)",
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.geniv = "eseqiv",
|
|
}
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
|
|
.cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
|
|
}, {
|
|
.crypto = {
|
|
.cra_name = "ecb(aes)",
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
}
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
|
|
.cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
|
|
}, {
|
|
.crypto = {
|
|
.cra_name = "ctr(aes)",
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.geniv = "eseqiv",
|
|
}
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
|
|
.cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
|
|
}, {
|
|
.crypto = {
|
|
.cra_name = "rfc3686(ctr(aes))",
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_u = { .ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.geniv = "eseqiv",
|
|
.setkey = ablk_rfc3686_setkey,
|
|
.encrypt = ablk_rfc3686_crypt,
|
|
.decrypt = ablk_rfc3686_crypt }
|
|
}
|
|
},
|
|
.cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
|
|
.cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
|
|
} };
|
|
|
|
static struct ixp_aead_alg ixp4xx_aeads[] = {
|
|
{
|
|
.crypto = {
|
|
.base = {
|
|
.cra_name = "authenc(hmac(md5),cbc(des))",
|
|
.cra_blocksize = DES_BLOCK_SIZE,
|
|
},
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.maxauthsize = MD5_DIGEST_SIZE,
|
|
},
|
|
.hash = &hash_alg_md5,
|
|
.cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
|
|
}, {
|
|
.crypto = {
|
|
.base = {
|
|
.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
},
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
.maxauthsize = MD5_DIGEST_SIZE,
|
|
},
|
|
.hash = &hash_alg_md5,
|
|
.cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
|
|
}, {
|
|
.crypto = {
|
|
.base = {
|
|
.cra_name = "authenc(hmac(sha1),cbc(des))",
|
|
.cra_blocksize = DES_BLOCK_SIZE,
|
|
},
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
|
},
|
|
.hash = &hash_alg_sha1,
|
|
.cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
|
|
}, {
|
|
.crypto = {
|
|
.base = {
|
|
.cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
|
|
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
|
|
},
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
|
},
|
|
.hash = &hash_alg_sha1,
|
|
.cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
|
|
.cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
|
|
}, {
|
|
.crypto = {
|
|
.base = {
|
|
.cra_name = "authenc(hmac(md5),cbc(aes))",
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
},
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.maxauthsize = MD5_DIGEST_SIZE,
|
|
},
|
|
.hash = &hash_alg_md5,
|
|
.cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
|
|
.cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
|
|
}, {
|
|
.crypto = {
|
|
.base = {
|
|
.cra_name = "authenc(hmac(sha1),cbc(aes))",
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
},
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
|
},
|
|
.hash = &hash_alg_sha1,
|
|
.cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
|
|
.cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
|
|
} };
|
|
|
|
#define IXP_POSTFIX "-ixp4xx"
|
|
|
|
static const struct platform_device_info ixp_dev_info __initdata = {
|
|
.name = DRIVER_NAME,
|
|
.id = 0,
|
|
.dma_mask = DMA_BIT_MASK(32),
|
|
};
|
|
|
|
static int __init ixp_module_init(void)
|
|
{
|
|
int num = ARRAY_SIZE(ixp4xx_algos);
|
|
int i, err;
|
|
|
|
pdev = platform_device_register_full(&ixp_dev_info);
|
|
if (IS_ERR(pdev))
|
|
return PTR_ERR(pdev);
|
|
|
|
spin_lock_init(&desc_lock);
|
|
spin_lock_init(&emerg_lock);
|
|
|
|
err = init_ixp_crypto(&pdev->dev);
|
|
if (err) {
|
|
platform_device_unregister(pdev);
|
|
return err;
|
|
}
|
|
for (i=0; i< num; i++) {
|
|
struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
|
|
|
|
if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
|
|
"%s"IXP_POSTFIX, cra->cra_name) >=
|
|
CRYPTO_MAX_ALG_NAME)
|
|
{
|
|
continue;
|
|
}
|
|
if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
|
|
continue;
|
|
}
|
|
|
|
/* block ciphers */
|
|
cra->cra_type = &crypto_ablkcipher_type;
|
|
cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
CRYPTO_ALG_ASYNC;
|
|
if (!cra->cra_ablkcipher.setkey)
|
|
cra->cra_ablkcipher.setkey = ablk_setkey;
|
|
if (!cra->cra_ablkcipher.encrypt)
|
|
cra->cra_ablkcipher.encrypt = ablk_encrypt;
|
|
if (!cra->cra_ablkcipher.decrypt)
|
|
cra->cra_ablkcipher.decrypt = ablk_decrypt;
|
|
cra->cra_init = init_tfm_ablk;
|
|
|
|
cra->cra_ctxsize = sizeof(struct ixp_ctx);
|
|
cra->cra_module = THIS_MODULE;
|
|
cra->cra_alignmask = 3;
|
|
cra->cra_priority = 300;
|
|
cra->cra_exit = exit_tfm;
|
|
if (crypto_register_alg(cra))
|
|
printk(KERN_ERR "Failed to register '%s'\n",
|
|
cra->cra_name);
|
|
else
|
|
ixp4xx_algos[i].registered = 1;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
|
|
struct aead_alg *cra = &ixp4xx_aeads[i].crypto;
|
|
|
|
if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
|
|
"%s"IXP_POSTFIX, cra->base.cra_name) >=
|
|
CRYPTO_MAX_ALG_NAME)
|
|
continue;
|
|
if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
|
|
continue;
|
|
|
|
/* authenc */
|
|
cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
CRYPTO_ALG_ASYNC;
|
|
cra->setkey = aead_setkey;
|
|
cra->setauthsize = aead_setauthsize;
|
|
cra->encrypt = aead_encrypt;
|
|
cra->decrypt = aead_decrypt;
|
|
cra->init = init_tfm_aead;
|
|
cra->exit = exit_tfm_aead;
|
|
|
|
cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
|
|
cra->base.cra_module = THIS_MODULE;
|
|
cra->base.cra_alignmask = 3;
|
|
cra->base.cra_priority = 300;
|
|
|
|
if (crypto_register_aead(cra))
|
|
printk(KERN_ERR "Failed to register '%s'\n",
|
|
cra->base.cra_driver_name);
|
|
else
|
|
ixp4xx_aeads[i].registered = 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void __exit ixp_module_exit(void)
|
|
{
|
|
int num = ARRAY_SIZE(ixp4xx_algos);
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
|
|
if (ixp4xx_aeads[i].registered)
|
|
crypto_unregister_aead(&ixp4xx_aeads[i].crypto);
|
|
}
|
|
|
|
for (i=0; i< num; i++) {
|
|
if (ixp4xx_algos[i].registered)
|
|
crypto_unregister_alg(&ixp4xx_algos[i].crypto);
|
|
}
|
|
release_ixp_crypto(&pdev->dev);
|
|
platform_device_unregister(pdev);
|
|
}
|
|
|
|
module_init(ixp_module_init);
|
|
module_exit(ixp_module_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
|
|
MODULE_DESCRIPTION("IXP4xx hardware crypto");
|
|
|