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baafb43537
Tegra hardware design cannot reliably support an arbitrary set of keys waking up the system. Modify wakeup logic so either any key wakes the system up or none will do. Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
800 lines
19 KiB
C
800 lines
19 KiB
C
/*
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* Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
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* keyboard controller
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*
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* Copyright (c) 2009-2011, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/input.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <mach/clk.h>
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#include <mach/kbc.h>
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#define KBC_MAX_DEBOUNCE_CNT 0x3ffu
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/* KBC row scan time and delay for beginning the row scan. */
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#define KBC_ROW_SCAN_TIME 16
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#define KBC_ROW_SCAN_DLY 5
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/* KBC uses a 32KHz clock so a cycle = 1/32Khz */
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#define KBC_CYCLE_USEC 32
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/* KBC Registers */
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/* KBC Control Register */
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#define KBC_CONTROL_0 0x0
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#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
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#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
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#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
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#define KBC_CONTROL_KBC_EN (1 << 0)
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/* KBC Interrupt Register */
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#define KBC_INT_0 0x4
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#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
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#define KBC_ROW_CFG0_0 0x8
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#define KBC_COL_CFG0_0 0x18
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#define KBC_INIT_DLY_0 0x28
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#define KBC_RPT_DLY_0 0x2c
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#define KBC_KP_ENT0_0 0x30
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#define KBC_KP_ENT1_0 0x34
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#define KBC_ROW0_MASK_0 0x38
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#define KBC_ROW_SHIFT 3
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struct tegra_kbc {
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void __iomem *mmio;
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struct input_dev *idev;
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unsigned int irq;
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spinlock_t lock;
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unsigned int repoll_dly;
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unsigned long cp_dly_jiffies;
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bool use_fn_map;
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bool use_ghost_filter;
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const struct tegra_kbc_platform_data *pdata;
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unsigned short keycode[KBC_MAX_KEY * 2];
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unsigned short current_keys[KBC_MAX_KPENT];
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unsigned int num_pressed_keys;
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struct timer_list timer;
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struct clk *clk;
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};
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static const u32 tegra_kbc_default_keymap[] = {
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KEY(0, 2, KEY_W),
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KEY(0, 3, KEY_S),
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KEY(0, 4, KEY_A),
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KEY(0, 5, KEY_Z),
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KEY(0, 7, KEY_FN),
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KEY(1, 7, KEY_LEFTMETA),
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KEY(2, 6, KEY_RIGHTALT),
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KEY(2, 7, KEY_LEFTALT),
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KEY(3, 0, KEY_5),
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KEY(3, 1, KEY_4),
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KEY(3, 2, KEY_R),
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KEY(3, 3, KEY_E),
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KEY(3, 4, KEY_F),
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KEY(3, 5, KEY_D),
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KEY(3, 6, KEY_X),
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KEY(4, 0, KEY_7),
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KEY(4, 1, KEY_6),
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KEY(4, 2, KEY_T),
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KEY(4, 3, KEY_H),
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KEY(4, 4, KEY_G),
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KEY(4, 5, KEY_V),
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KEY(4, 6, KEY_C),
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KEY(4, 7, KEY_SPACE),
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KEY(5, 0, KEY_9),
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KEY(5, 1, KEY_8),
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KEY(5, 2, KEY_U),
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KEY(5, 3, KEY_Y),
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KEY(5, 4, KEY_J),
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KEY(5, 5, KEY_N),
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KEY(5, 6, KEY_B),
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KEY(5, 7, KEY_BACKSLASH),
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KEY(6, 0, KEY_MINUS),
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KEY(6, 1, KEY_0),
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KEY(6, 2, KEY_O),
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KEY(6, 3, KEY_I),
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KEY(6, 4, KEY_L),
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KEY(6, 5, KEY_K),
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KEY(6, 6, KEY_COMMA),
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KEY(6, 7, KEY_M),
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KEY(7, 1, KEY_EQUAL),
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KEY(7, 2, KEY_RIGHTBRACE),
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KEY(7, 3, KEY_ENTER),
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KEY(7, 7, KEY_MENU),
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KEY(8, 4, KEY_RIGHTSHIFT),
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KEY(8, 5, KEY_LEFTSHIFT),
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KEY(9, 5, KEY_RIGHTCTRL),
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KEY(9, 7, KEY_LEFTCTRL),
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KEY(11, 0, KEY_LEFTBRACE),
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KEY(11, 1, KEY_P),
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KEY(11, 2, KEY_APOSTROPHE),
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KEY(11, 3, KEY_SEMICOLON),
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KEY(11, 4, KEY_SLASH),
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KEY(11, 5, KEY_DOT),
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KEY(12, 0, KEY_F10),
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KEY(12, 1, KEY_F9),
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KEY(12, 2, KEY_BACKSPACE),
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KEY(12, 3, KEY_3),
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KEY(12, 4, KEY_2),
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KEY(12, 5, KEY_UP),
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KEY(12, 6, KEY_PRINT),
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KEY(12, 7, KEY_PAUSE),
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KEY(13, 0, KEY_INSERT),
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KEY(13, 1, KEY_DELETE),
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KEY(13, 3, KEY_PAGEUP),
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KEY(13, 4, KEY_PAGEDOWN),
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KEY(13, 5, KEY_RIGHT),
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KEY(13, 6, KEY_DOWN),
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KEY(13, 7, KEY_LEFT),
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KEY(14, 0, KEY_F11),
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KEY(14, 1, KEY_F12),
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KEY(14, 2, KEY_F8),
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KEY(14, 3, KEY_Q),
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KEY(14, 4, KEY_F4),
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KEY(14, 5, KEY_F3),
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KEY(14, 6, KEY_1),
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KEY(14, 7, KEY_F7),
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KEY(15, 0, KEY_ESC),
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KEY(15, 1, KEY_GRAVE),
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KEY(15, 2, KEY_F5),
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KEY(15, 3, KEY_TAB),
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KEY(15, 4, KEY_F1),
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KEY(15, 5, KEY_F2),
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KEY(15, 6, KEY_CAPSLOCK),
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KEY(15, 7, KEY_F6),
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/* Software Handled Function Keys */
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KEY(20, 0, KEY_KP7),
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KEY(21, 0, KEY_KP9),
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KEY(21, 1, KEY_KP8),
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KEY(21, 2, KEY_KP4),
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KEY(21, 4, KEY_KP1),
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KEY(22, 1, KEY_KPSLASH),
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KEY(22, 2, KEY_KP6),
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KEY(22, 3, KEY_KP5),
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KEY(22, 4, KEY_KP3),
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KEY(22, 5, KEY_KP2),
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KEY(22, 7, KEY_KP0),
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KEY(27, 1, KEY_KPASTERISK),
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KEY(27, 3, KEY_KPMINUS),
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KEY(27, 4, KEY_KPPLUS),
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KEY(27, 5, KEY_KPDOT),
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KEY(28, 5, KEY_VOLUMEUP),
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KEY(29, 3, KEY_HOME),
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KEY(29, 4, KEY_END),
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KEY(29, 5, KEY_BRIGHTNESSDOWN),
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KEY(29, 6, KEY_VOLUMEDOWN),
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KEY(29, 7, KEY_BRIGHTNESSUP),
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KEY(30, 0, KEY_NUMLOCK),
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KEY(30, 1, KEY_SCROLLLOCK),
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KEY(30, 2, KEY_MUTE),
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KEY(31, 4, KEY_HELP),
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};
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static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
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.keymap = tegra_kbc_default_keymap,
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.keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
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};
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static void tegra_kbc_report_released_keys(struct input_dev *input,
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unsigned short old_keycodes[],
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unsigned int old_num_keys,
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unsigned short new_keycodes[],
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unsigned int new_num_keys)
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{
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unsigned int i, j;
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for (i = 0; i < old_num_keys; i++) {
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for (j = 0; j < new_num_keys; j++)
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if (old_keycodes[i] == new_keycodes[j])
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break;
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if (j == new_num_keys)
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input_report_key(input, old_keycodes[i], 0);
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}
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}
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static void tegra_kbc_report_pressed_keys(struct input_dev *input,
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unsigned char scancodes[],
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unsigned short keycodes[],
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unsigned int num_pressed_keys)
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{
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unsigned int i;
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for (i = 0; i < num_pressed_keys; i++) {
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input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
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input_report_key(input, keycodes[i], 1);
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}
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}
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static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
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{
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unsigned char scancodes[KBC_MAX_KPENT];
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unsigned short keycodes[KBC_MAX_KPENT];
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u32 val = 0;
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unsigned int i;
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unsigned int num_down = 0;
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unsigned long flags;
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bool fn_keypress = false;
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bool key_in_same_row = false;
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bool key_in_same_col = false;
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spin_lock_irqsave(&kbc->lock, flags);
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for (i = 0; i < KBC_MAX_KPENT; i++) {
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if ((i % 4) == 0)
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val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
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if (val & 0x80) {
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unsigned int col = val & 0x07;
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unsigned int row = (val >> 3) & 0x0f;
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unsigned char scancode =
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MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
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scancodes[num_down] = scancode;
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keycodes[num_down] = kbc->keycode[scancode];
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/* If driver uses Fn map, do not report the Fn key. */
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if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
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fn_keypress = true;
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else
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num_down++;
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}
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val >>= 8;
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}
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/*
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* Matrix keyboard designs are prone to keyboard ghosting.
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* Ghosting occurs if there are 3 keys such that -
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* any 2 of the 3 keys share a row, and any 2 of them share a column.
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* If so ignore the key presses for this iteration.
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*/
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if ((kbc->use_ghost_filter) && (num_down >= 3)) {
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for (i = 0; i < num_down; i++) {
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unsigned int j;
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u8 curr_col = scancodes[i] & 0x07;
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u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
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/*
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* Find 2 keys such that one key is in the same row
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* and the other is in the same column as the i-th key.
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*/
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for (j = i + 1; j < num_down; j++) {
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u8 col = scancodes[j] & 0x07;
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u8 row = scancodes[j] >> KBC_ROW_SHIFT;
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if (col == curr_col)
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key_in_same_col = true;
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if (row == curr_row)
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key_in_same_row = true;
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}
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}
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}
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/*
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* If the platform uses Fn keymaps, translate keys on a Fn keypress.
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* Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
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*/
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if (fn_keypress) {
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for (i = 0; i < num_down; i++) {
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scancodes[i] += KBC_MAX_KEY;
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keycodes[i] = kbc->keycode[scancodes[i]];
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}
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}
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spin_unlock_irqrestore(&kbc->lock, flags);
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/* Ignore the key presses for this iteration? */
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if (key_in_same_col && key_in_same_row)
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return;
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tegra_kbc_report_released_keys(kbc->idev,
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kbc->current_keys, kbc->num_pressed_keys,
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keycodes, num_down);
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tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
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input_sync(kbc->idev);
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memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
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kbc->num_pressed_keys = num_down;
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}
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static void tegra_kbc_keypress_timer(unsigned long data)
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{
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struct tegra_kbc *kbc = (struct tegra_kbc *)data;
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unsigned long flags;
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u32 val;
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unsigned int i;
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val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
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if (val) {
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unsigned long dly;
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tegra_kbc_report_keys(kbc);
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/*
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* If more than one keys are pressed we need not wait
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* for the repoll delay.
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*/
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dly = (val == 1) ? kbc->repoll_dly : 1;
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mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
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} else {
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/* Release any pressed keys and exit the polling loop */
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for (i = 0; i < kbc->num_pressed_keys; i++)
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input_report_key(kbc->idev, kbc->current_keys[i], 0);
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input_sync(kbc->idev);
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kbc->num_pressed_keys = 0;
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/* All keys are released so enable the keypress interrupt */
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spin_lock_irqsave(&kbc->lock, flags);
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val = readl(kbc->mmio + KBC_CONTROL_0);
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val |= KBC_CONTROL_FIFO_CNT_INT_EN;
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writel(val, kbc->mmio + KBC_CONTROL_0);
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spin_unlock_irqrestore(&kbc->lock, flags);
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}
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}
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static irqreturn_t tegra_kbc_isr(int irq, void *args)
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{
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struct tegra_kbc *kbc = args;
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u32 val, ctl;
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/*
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* Until all keys are released, defer further processing to
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* the polling loop in tegra_kbc_keypress_timer
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*/
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ctl = readl(kbc->mmio + KBC_CONTROL_0);
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ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
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writel(ctl, kbc->mmio + KBC_CONTROL_0);
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/*
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* Quickly bail out & reenable interrupts if the fifo threshold
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* count interrupt wasn't the interrupt source
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*/
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val = readl(kbc->mmio + KBC_INT_0);
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writel(val, kbc->mmio + KBC_INT_0);
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if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
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/*
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* Schedule timer to run when hardware is in continuous
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* polling mode.
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*/
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mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
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} else {
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ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
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writel(ctl, kbc->mmio + KBC_CONTROL_0);
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}
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return IRQ_HANDLED;
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}
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static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
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{
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const struct tegra_kbc_platform_data *pdata = kbc->pdata;
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int i;
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unsigned int rst_val;
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/* Either mask all keys or none. */
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rst_val = (filter && !pdata->wakeup) ? ~0 : 0;
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for (i = 0; i < KBC_MAX_ROW; i++)
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writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
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}
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static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
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{
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const struct tegra_kbc_platform_data *pdata = kbc->pdata;
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int i;
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for (i = 0; i < KBC_MAX_GPIO; i++) {
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u32 r_shft = 5 * (i % 6);
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u32 c_shft = 4 * (i % 8);
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u32 r_mask = 0x1f << r_shft;
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u32 c_mask = 0x0f << c_shft;
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u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
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u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
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u32 row_cfg = readl(kbc->mmio + r_offs);
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u32 col_cfg = readl(kbc->mmio + c_offs);
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row_cfg &= ~r_mask;
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col_cfg &= ~c_mask;
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if (pdata->pin_cfg[i].is_row)
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row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
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else
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col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
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writel(row_cfg, kbc->mmio + r_offs);
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writel(col_cfg, kbc->mmio + c_offs);
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}
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}
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static int tegra_kbc_start(struct tegra_kbc *kbc)
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{
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const struct tegra_kbc_platform_data *pdata = kbc->pdata;
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unsigned long flags;
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unsigned int debounce_cnt;
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u32 val = 0;
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clk_enable(kbc->clk);
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/* Reset the KBC controller to clear all previous status.*/
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tegra_periph_reset_assert(kbc->clk);
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udelay(100);
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tegra_periph_reset_deassert(kbc->clk);
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udelay(100);
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tegra_kbc_config_pins(kbc);
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tegra_kbc_setup_wakekeys(kbc, false);
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writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
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/* Keyboard debounce count is maximum of 12 bits. */
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debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
|
|
val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
|
|
val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
|
|
val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
|
|
val |= KBC_CONTROL_KBC_EN; /* enable */
|
|
writel(val, kbc->mmio + KBC_CONTROL_0);
|
|
|
|
/*
|
|
* Compute the delay(ns) from interrupt mode to continuous polling
|
|
* mode so the timer routine is scheduled appropriately.
|
|
*/
|
|
val = readl(kbc->mmio + KBC_INIT_DLY_0);
|
|
kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
|
|
|
|
kbc->num_pressed_keys = 0;
|
|
|
|
/*
|
|
* Atomically clear out any remaining entries in the key FIFO
|
|
* and enable keyboard interrupts.
|
|
*/
|
|
spin_lock_irqsave(&kbc->lock, flags);
|
|
while (1) {
|
|
val = readl(kbc->mmio + KBC_INT_0);
|
|
val >>= 4;
|
|
if (!val)
|
|
break;
|
|
|
|
val = readl(kbc->mmio + KBC_KP_ENT0_0);
|
|
val = readl(kbc->mmio + KBC_KP_ENT1_0);
|
|
}
|
|
writel(0x7, kbc->mmio + KBC_INT_0);
|
|
spin_unlock_irqrestore(&kbc->lock, flags);
|
|
|
|
enable_irq(kbc->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_kbc_stop(struct tegra_kbc *kbc)
|
|
{
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&kbc->lock, flags);
|
|
val = readl(kbc->mmio + KBC_CONTROL_0);
|
|
val &= ~1;
|
|
writel(val, kbc->mmio + KBC_CONTROL_0);
|
|
spin_unlock_irqrestore(&kbc->lock, flags);
|
|
|
|
disable_irq(kbc->irq);
|
|
del_timer_sync(&kbc->timer);
|
|
|
|
clk_disable(kbc->clk);
|
|
}
|
|
|
|
static int tegra_kbc_open(struct input_dev *dev)
|
|
{
|
|
struct tegra_kbc *kbc = input_get_drvdata(dev);
|
|
|
|
return tegra_kbc_start(kbc);
|
|
}
|
|
|
|
static void tegra_kbc_close(struct input_dev *dev)
|
|
{
|
|
struct tegra_kbc *kbc = input_get_drvdata(dev);
|
|
|
|
return tegra_kbc_stop(kbc);
|
|
}
|
|
|
|
static bool __devinit
|
|
tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
|
|
struct device *dev, unsigned int *num_rows)
|
|
{
|
|
int i;
|
|
|
|
*num_rows = 0;
|
|
|
|
for (i = 0; i < KBC_MAX_GPIO; i++) {
|
|
const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
|
|
|
|
if (pin_cfg->is_row) {
|
|
if (pin_cfg->num >= KBC_MAX_ROW) {
|
|
dev_err(dev,
|
|
"pin_cfg[%d]: invalid row number %d\n",
|
|
i, pin_cfg->num);
|
|
return false;
|
|
}
|
|
(*num_rows)++;
|
|
} else {
|
|
if (pin_cfg->num >= KBC_MAX_COL) {
|
|
dev_err(dev,
|
|
"pin_cfg[%d]: invalid column number %d\n",
|
|
i, pin_cfg->num);
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static int __devinit tegra_kbc_probe(struct platform_device *pdev)
|
|
{
|
|
const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
|
|
const struct matrix_keymap_data *keymap_data;
|
|
struct tegra_kbc *kbc;
|
|
struct input_dev *input_dev;
|
|
struct resource *res;
|
|
int irq;
|
|
int err;
|
|
int num_rows = 0;
|
|
unsigned int debounce_cnt;
|
|
unsigned int scan_time_rows;
|
|
|
|
if (!pdata)
|
|
return -EINVAL;
|
|
|
|
if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
|
|
return -EINVAL;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "failed to get I/O memory\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
|
|
input_dev = input_allocate_device();
|
|
if (!kbc || !input_dev) {
|
|
err = -ENOMEM;
|
|
goto err_free_mem;
|
|
}
|
|
|
|
kbc->pdata = pdata;
|
|
kbc->idev = input_dev;
|
|
kbc->irq = irq;
|
|
spin_lock_init(&kbc->lock);
|
|
setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
|
|
|
|
res = request_mem_region(res->start, resource_size(res), pdev->name);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "failed to request I/O memory\n");
|
|
err = -EBUSY;
|
|
goto err_free_mem;
|
|
}
|
|
|
|
kbc->mmio = ioremap(res->start, resource_size(res));
|
|
if (!kbc->mmio) {
|
|
dev_err(&pdev->dev, "failed to remap I/O memory\n");
|
|
err = -ENXIO;
|
|
goto err_free_mem_region;
|
|
}
|
|
|
|
kbc->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(kbc->clk)) {
|
|
dev_err(&pdev->dev, "failed to get keyboard clock\n");
|
|
err = PTR_ERR(kbc->clk);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
/*
|
|
* The time delay between two consecutive reads of the FIFO is
|
|
* the sum of the repeat time and the time taken for scanning
|
|
* the rows. There is an additional delay before the row scanning
|
|
* starts. The repoll delay is computed in milliseconds.
|
|
*/
|
|
debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
|
|
scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
|
|
kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
|
|
kbc->repoll_dly = ((kbc->repoll_dly * KBC_CYCLE_USEC) + 999) / 1000;
|
|
|
|
input_dev->name = pdev->name;
|
|
input_dev->id.bustype = BUS_HOST;
|
|
input_dev->dev.parent = &pdev->dev;
|
|
input_dev->open = tegra_kbc_open;
|
|
input_dev->close = tegra_kbc_close;
|
|
|
|
input_set_drvdata(input_dev, kbc);
|
|
|
|
input_dev->evbit[0] = BIT_MASK(EV_KEY);
|
|
input_set_capability(input_dev, EV_MSC, MSC_SCAN);
|
|
|
|
input_dev->keycode = kbc->keycode;
|
|
input_dev->keycodesize = sizeof(kbc->keycode[0]);
|
|
input_dev->keycodemax = KBC_MAX_KEY;
|
|
if (pdata->use_fn_map)
|
|
input_dev->keycodemax *= 2;
|
|
|
|
kbc->use_fn_map = pdata->use_fn_map;
|
|
kbc->use_ghost_filter = pdata->use_ghost_filter;
|
|
keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
|
|
matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
|
|
input_dev->keycode, input_dev->keybit);
|
|
|
|
err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
|
|
pdev->name, kbc);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
|
|
goto err_put_clk;
|
|
}
|
|
|
|
disable_irq(kbc->irq);
|
|
|
|
err = input_register_device(kbc->idev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to register input device\n");
|
|
goto err_free_irq;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, kbc);
|
|
device_init_wakeup(&pdev->dev, pdata->wakeup);
|
|
|
|
return 0;
|
|
|
|
err_free_irq:
|
|
free_irq(kbc->irq, pdev);
|
|
err_put_clk:
|
|
clk_put(kbc->clk);
|
|
err_iounmap:
|
|
iounmap(kbc->mmio);
|
|
err_free_mem_region:
|
|
release_mem_region(res->start, resource_size(res));
|
|
err_free_mem:
|
|
input_free_device(kbc->idev);
|
|
kfree(kbc);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int __devexit tegra_kbc_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
|
struct resource *res;
|
|
|
|
free_irq(kbc->irq, pdev);
|
|
clk_put(kbc->clk);
|
|
|
|
input_unregister_device(kbc->idev);
|
|
iounmap(kbc->mmio);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(res->start, resource_size(res));
|
|
|
|
kfree(kbc);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int tegra_kbc_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
|
|
|
if (device_may_wakeup(&pdev->dev)) {
|
|
tegra_kbc_setup_wakekeys(kbc, true);
|
|
enable_irq_wake(kbc->irq);
|
|
/* Forcefully clear the interrupt status */
|
|
writel(0x7, kbc->mmio + KBC_INT_0);
|
|
msleep(30);
|
|
} else {
|
|
mutex_lock(&kbc->idev->mutex);
|
|
if (kbc->idev->users)
|
|
tegra_kbc_stop(kbc);
|
|
mutex_unlock(&kbc->idev->mutex);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_kbc_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
|
int err = 0;
|
|
|
|
if (device_may_wakeup(&pdev->dev)) {
|
|
disable_irq_wake(kbc->irq);
|
|
tegra_kbc_setup_wakekeys(kbc, false);
|
|
} else {
|
|
mutex_lock(&kbc->idev->mutex);
|
|
if (kbc->idev->users)
|
|
err = tegra_kbc_start(kbc);
|
|
mutex_unlock(&kbc->idev->mutex);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
|
|
|
|
static struct platform_driver tegra_kbc_driver = {
|
|
.probe = tegra_kbc_probe,
|
|
.remove = __devexit_p(tegra_kbc_remove),
|
|
.driver = {
|
|
.name = "tegra-kbc",
|
|
.owner = THIS_MODULE,
|
|
.pm = &tegra_kbc_pm_ops,
|
|
},
|
|
};
|
|
|
|
static void __exit tegra_kbc_exit(void)
|
|
{
|
|
platform_driver_unregister(&tegra_kbc_driver);
|
|
}
|
|
module_exit(tegra_kbc_exit);
|
|
|
|
static int __init tegra_kbc_init(void)
|
|
{
|
|
return platform_driver_register(&tegra_kbc_driver);
|
|
}
|
|
module_init(tegra_kbc_init);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
|
|
MODULE_ALIAS("platform:tegra-kbc");
|