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The Allwinner A31 and A23 SoCs have a reset controller maintaining the UART in reset by default. This patch adds optional reset support to the driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
58 lines
1.5 KiB
Plaintext
58 lines
1.5 KiB
Plaintext
* Synopsys DesignWare ABP UART
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Required properties:
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- compatible : "snps,dw-apb-uart"
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- reg : offset and length of the register set for the device.
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- interrupts : should contain uart interrupt.
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Clock handling:
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The clock rate of the input clock needs to be supplied by one of
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- clock-frequency : the input clock frequency for the UART.
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- clocks : phandle to the input clock
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The supplying peripheral clock can also be handled, needing a second property
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- clock-names: tuple listing input clock names.
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Required elements: "baudclk", "apb_pclk"
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Optional properties:
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- resets : phandle to the parent reset controller.
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- reg-shift : quantity to shift the register offsets by. If this property is
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not present then the register offsets are not shifted.
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- reg-io-width : the size (in bytes) of the IO accesses that should be
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performed on the device. If this property is not present then single byte
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accesses are used.
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Example:
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uart@80230000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x80230000 0x100>;
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clock-frequency = <3686400>;
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interrupts = <10>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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Example with one clock:
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uart@80230000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x80230000 0x100>;
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clocks = <&baudclk>;
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interrupts = <10>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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Example with two clocks:
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uart@80230000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x80230000 0x100>;
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clocks = <&baudclk>, <&apb_pclk>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <10>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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