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1a5b537644
This commit introduces a generic device tree binding for
IOMMU devices. Only a very minimal subset is described
here, but it is enough to cover the requirements of both the
Exynos System MMU and Tegra SMMU as discussed here:
https://lkml.org/lkml/2014/4/27/346
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Olof Johansson <olof@lixom.net>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
183 lines
6.0 KiB
Plaintext
183 lines
6.0 KiB
Plaintext
This document describes the generic device tree binding for IOMMUs and their
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master(s).
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IOMMU device node:
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==================
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An IOMMU can provide the following services:
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* Remap address space to allow devices to access physical memory ranges that
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they otherwise wouldn't be capable of accessing.
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Example: 32-bit DMA to 64-bit physical addresses
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* Implement scatter-gather at page level granularity so that the device does
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not have to.
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* Provide system protection against "rogue" DMA by forcing all accesses to go
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through the IOMMU and faulting when encountering accesses to unmapped
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address regions.
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* Provide address space isolation between multiple contexts.
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Example: Virtualization
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Device nodes compatible with this binding represent hardware with some of the
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above capabilities.
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IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
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typically have a fixed association to the master device, whereas multiple-
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master IOMMU devices can translate accesses from more than one master.
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The device tree node of the IOMMU device's parent bus must contain a valid
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"dma-ranges" property that describes how the physical address space of the
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IOMMU maps to memory. An empty "dma-ranges" property means that there is a
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1:1 mapping from IOMMU to memory.
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Required properties:
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--------------------
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- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
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address.
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The meaning of the IOMMU specifier is defined by the device tree binding of
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the specific IOMMU. Below are a few examples of typical use-cases:
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- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
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therefore no additional information needs to be encoded in the specifier.
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This may also apply to multiple master IOMMU devices that do not allow the
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association of masters to be configured. Note that an IOMMU can by design
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be multi-master yet only expose a single master in a given configuration.
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In such cases the number of cells will usually be 1 as in the next case.
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- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
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in order to enable translation for a given master. In such cases the single
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address cell corresponds to the master device's ID. In some cases more than
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one cell can be required to represent a single master ID.
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- #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
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be configured. The first cell of the address in this may contain the master
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device's ID for example, while the second cell could contain the start of
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the DMA window for the given device. The length of the DMA window is given
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by the third and fourth cells.
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Note that these are merely examples and real-world use-cases may use different
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definitions to represent their individual needs. Always refer to the specific
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IOMMU binding for the exact meaning of the cells that make up the specifier.
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IOMMU master node:
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==================
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Devices that access memory through an IOMMU are called masters. A device can
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have multiple master interfaces (to one or more IOMMU devices).
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Required properties:
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--------------------
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- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
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master interfaces of the device. One entry in the list describes one master
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interface of the device.
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When an "iommus" property is specified in a device tree node, the IOMMU will
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be used for address translation. If a "dma-ranges" property exists in the
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device's parent node it will be ignored. An exception to this rule is if the
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referenced IOMMU is disabled, in which case the "dma-ranges" property of the
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parent shall take effect. Note that merely disabling a device tree node does
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not guarantee that the IOMMU is really disabled since the hardware may not
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have a means to turn off translation. But it is invalid in such cases to
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disable the IOMMU's device tree node in the first place because it would
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prevent any driver from properly setting up the translations.
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Notes:
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======
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One possible extension to the above is to use an "iommus" property along with
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a "dma-ranges" property in a bus device node (such as PCI host bridges). This
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can be useful to describe how children on the bus relate to the IOMMU if they
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are not explicitly listed in the device tree (e.g. PCI devices). However, the
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requirements of that use-case haven't been fully determined yet. Implementing
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this is therefore not recommended without further discussion and extension of
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this binding.
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Examples:
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=========
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Single-master IOMMU:
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--------------------
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iommu {
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#iommu-cells = <0>;
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};
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master {
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iommus = <&{/iommu}>;
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};
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Multiple-master IOMMU with fixed associations:
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----------------------------------------------
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/* multiple-master IOMMU */
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iommu {
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/*
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* Masters are statically associated with this IOMMU and share
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* the same address translations because the IOMMU does not
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* have sufficient information to distinguish between masters.
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*
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* Consequently address translation is always on or off for
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* all masters at any given point in time.
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*/
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#iommu-cells = <0>;
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};
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/* static association with IOMMU */
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master@1 {
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reg = <1>;
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iommus = <&{/iommu}>;
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};
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/* static association with IOMMU */
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master@2 {
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reg = <2>;
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iommus = <&{/iommu}>;
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};
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Multiple-master IOMMU:
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----------------------
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iommu {
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/* the specifier represents the ID of the master */
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#iommu-cells = <1>;
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};
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master@1 {
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/* device has master ID 42 in the IOMMU */
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iommus = <&{/iommu} 42>;
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};
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master@2 {
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/* device has master IDs 23 and 24 in the IOMMU */
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iommus = <&{/iommu} 23>, <&{/iommu} 24>;
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};
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Multiple-master IOMMU with configurable DMA window:
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---------------------------------------------------
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/ {
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iommu {
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/*
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* One cell for the master ID and one cell for the
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* address of the DMA window. The length of the DMA
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* window is encoded in two cells.
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*
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* The DMA window is the range addressable by the
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* master (i.e. the I/O virtual address space).
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*/
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#iommu-cells = <4>;
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};
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master {
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/* master ID 42, 4 GiB DMA window starting at 0 */
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iommus = <&{/iommu} 42 0 0x1 0x0>;
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};
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};
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