mirror of
https://github.com/torvalds/linux.git
synced 2024-11-22 12:11:40 +00:00
1ad3f701c3
CXL PMU devices can be found from entries in the Register Locator DVSEC. Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230526095824.16336-4-Jonathan.Cameron@huawei.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
29 lines
656 B
C
29 lines
656 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright(c) 2023 Huawei
|
|
* CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface)
|
|
*/
|
|
#ifndef CXL_PMU_H
|
|
#define CXL_PMU_H
|
|
#include <linux/device.h>
|
|
|
|
enum cxl_pmu_type {
|
|
CXL_PMU_MEMDEV,
|
|
};
|
|
|
|
#define CXL_PMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */
|
|
struct cxl_pmu {
|
|
struct device dev;
|
|
void __iomem *base;
|
|
int assoc_id;
|
|
int index;
|
|
enum cxl_pmu_type type;
|
|
};
|
|
|
|
#define to_cxl_pmu(dev) container_of(dev, struct cxl_pmu, dev)
|
|
struct cxl_pmu_regs;
|
|
int devm_cxl_pmu_add(struct device *parent, struct cxl_pmu_regs *regs,
|
|
int assoc_id, int idx, enum cxl_pmu_type type);
|
|
|
|
#endif
|