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96a388de5d
Move the headers to include/asm-x86 and fixup the header install make rules Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
245 lines
6.4 KiB
C
245 lines
6.4 KiB
C
#ifndef __ARCH_DESC_H
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#define __ARCH_DESC_H
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#include <asm/ldt.h>
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#include <asm/segment.h>
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#ifndef __ASSEMBLY__
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#include <linux/preempt.h>
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#include <linux/smp.h>
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#include <linux/percpu.h>
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#include <asm/mmu.h>
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struct Xgt_desc_struct {
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unsigned short size;
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unsigned long address __attribute__((packed));
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unsigned short pad;
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} __attribute__ ((packed));
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struct gdt_page
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{
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struct desc_struct gdt[GDT_ENTRIES];
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} __attribute__((aligned(PAGE_SIZE)));
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DECLARE_PER_CPU(struct gdt_page, gdt_page);
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static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
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{
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return per_cpu(gdt_page, cpu).gdt;
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}
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extern struct Xgt_desc_struct idt_descr;
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extern struct desc_struct idt_table[];
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extern void set_intr_gate(unsigned int irq, void * addr);
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static inline void pack_descriptor(__u32 *a, __u32 *b,
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unsigned long base, unsigned long limit, unsigned char type, unsigned char flags)
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{
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*a = ((base & 0xffff) << 16) | (limit & 0xffff);
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*b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
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(limit & 0x000f0000) | ((type & 0xff) << 8) | ((flags & 0xf) << 20);
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}
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static inline void pack_gate(__u32 *a, __u32 *b,
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unsigned long base, unsigned short seg, unsigned char type, unsigned char flags)
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{
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*a = (seg << 16) | (base & 0xffff);
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*b = (base & 0xffff0000) | ((type & 0xff) << 8) | (flags & 0xff);
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}
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#define DESCTYPE_LDT 0x82 /* present, system, DPL-0, LDT */
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#define DESCTYPE_TSS 0x89 /* present, system, DPL-0, 32-bit TSS */
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#define DESCTYPE_TASK 0x85 /* present, system, DPL-0, task gate */
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#define DESCTYPE_INT 0x8e /* present, system, DPL-0, interrupt gate */
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#define DESCTYPE_TRAP 0x8f /* present, system, DPL-0, trap gate */
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#define DESCTYPE_DPL3 0x60 /* DPL-3 */
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#define DESCTYPE_S 0x10 /* !system */
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define load_TR_desc() native_load_tr_desc()
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#define load_gdt(dtr) native_load_gdt(dtr)
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#define load_idt(dtr) native_load_idt(dtr)
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#define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr))
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#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt))
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#define store_gdt(dtr) native_store_gdt(dtr)
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#define store_idt(dtr) native_store_idt(dtr)
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#define store_tr(tr) (tr = native_store_tr())
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#define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt))
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#define load_TLS(t, cpu) native_load_tls(t, cpu)
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#define set_ldt native_set_ldt
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#define write_ldt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
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#define write_gdt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
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#define write_idt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
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#endif
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static inline void write_dt_entry(struct desc_struct *dt,
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int entry, u32 entry_low, u32 entry_high)
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{
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dt[entry].a = entry_low;
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dt[entry].b = entry_high;
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}
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static inline void native_set_ldt(const void *addr, unsigned int entries)
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{
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if (likely(entries == 0))
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__asm__ __volatile__("lldt %w0"::"q" (0));
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else {
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unsigned cpu = smp_processor_id();
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__u32 a, b;
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pack_descriptor(&a, &b, (unsigned long)addr,
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entries * sizeof(struct desc_struct) - 1,
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DESCTYPE_LDT, 0);
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write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, a, b);
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__asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
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}
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}
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static inline void native_load_tr_desc(void)
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{
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asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
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}
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static inline void native_load_gdt(const struct Xgt_desc_struct *dtr)
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{
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asm volatile("lgdt %0"::"m" (*dtr));
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}
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static inline void native_load_idt(const struct Xgt_desc_struct *dtr)
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{
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asm volatile("lidt %0"::"m" (*dtr));
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}
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static inline void native_store_gdt(struct Xgt_desc_struct *dtr)
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{
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asm ("sgdt %0":"=m" (*dtr));
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}
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static inline void native_store_idt(struct Xgt_desc_struct *dtr)
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{
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asm ("sidt %0":"=m" (*dtr));
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}
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static inline unsigned long native_store_tr(void)
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{
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unsigned long tr;
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asm ("str %0":"=r" (tr));
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return tr;
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}
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static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
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{
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unsigned int i;
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struct desc_struct *gdt = get_cpu_gdt_table(cpu);
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for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
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gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
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}
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static inline void _set_gate(int gate, unsigned int type, void *addr, unsigned short seg)
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{
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__u32 a, b;
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pack_gate(&a, &b, (unsigned long)addr, seg, type, 0);
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write_idt_entry(idt_table, gate, a, b);
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}
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static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, const void *addr)
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{
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__u32 a, b;
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pack_descriptor(&a, &b, (unsigned long)addr,
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offsetof(struct tss_struct, __cacheline_filler) - 1,
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DESCTYPE_TSS, 0);
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write_gdt_entry(get_cpu_gdt_table(cpu), entry, a, b);
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}
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#define set_tss_desc(cpu,addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
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#define LDT_entry_a(info) \
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((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
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#define LDT_entry_b(info) \
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(((info)->base_addr & 0xff000000) | \
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(((info)->base_addr & 0x00ff0000) >> 16) | \
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((info)->limit & 0xf0000) | \
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(((info)->read_exec_only ^ 1) << 9) | \
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((info)->contents << 10) | \
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(((info)->seg_not_present ^ 1) << 15) | \
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((info)->seg_32bit << 22) | \
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((info)->limit_in_pages << 23) | \
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((info)->useable << 20) | \
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0x7000)
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#define LDT_empty(info) (\
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(info)->base_addr == 0 && \
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(info)->limit == 0 && \
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(info)->contents == 0 && \
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(info)->read_exec_only == 1 && \
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(info)->seg_32bit == 0 && \
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(info)->limit_in_pages == 0 && \
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(info)->seg_not_present == 1 && \
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(info)->useable == 0 )
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static inline void clear_LDT(void)
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{
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set_ldt(NULL, 0);
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}
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/*
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* load one particular LDT into the current CPU
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*/
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static inline void load_LDT_nolock(mm_context_t *pc)
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{
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set_ldt(pc->ldt, pc->size);
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}
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static inline void load_LDT(mm_context_t *pc)
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{
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preempt_disable();
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load_LDT_nolock(pc);
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preempt_enable();
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}
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static inline unsigned long get_desc_base(unsigned long *desc)
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{
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unsigned long base;
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base = ((desc[0] >> 16) & 0x0000ffff) |
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((desc[1] << 16) & 0x00ff0000) |
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(desc[1] & 0xff000000);
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return base;
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}
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#else /* __ASSEMBLY__ */
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/*
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* GET_DESC_BASE reads the descriptor base of the specified segment.
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*
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* Args:
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* idx - descriptor index
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* gdt - GDT pointer
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* base - 32bit register to which the base will be written
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* lo_w - lo word of the "base" register
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* lo_b - lo byte of the "base" register
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* hi_b - hi byte of the low word of the "base" register
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*
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* Example:
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* GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
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* Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
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*/
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#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
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movb idx*8+4(gdt), lo_b; \
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movb idx*8+7(gdt), hi_b; \
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shll $16, base; \
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movw idx*8+2(gdt), lo_w;
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#endif /* !__ASSEMBLY__ */
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#endif
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