mirror of
https://github.com/torvalds/linux.git
synced 2024-11-05 19:41:54 +00:00
52caa59ed3
Pull i2c updates from Wolfram Sang:
"Highlights:
- new drivers for Intel ismt & Broadcom bcm2835
- a number of drivers got support for more variants and mostly got
cleaned up on the way (sis630, i801, at91, tegra, designware)
- i2c got rid of all *_set_drvdata(..., NULL) on remove/probe failure
- removed the i2c_smbus_process_call from the core since there are no
users
- mxs can now switch between PIO and DMA depending on the message
size and the bus speed can now be arbitrary
In addition, there is the usual bunch of fixes, cleanups, devm_*
conversions, etc"
Fixed conflict (and buggy devm_* conversion) in i2c-s3c2410.c
* 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (39 commits)
i2c: Remove unneeded xxx_set_drvdata(..., NULL) calls
i2c: pxa: remove incorrect __exit annotations
i2c: ocores: Fix pointer to integer cast warning
i2c: tegra: remove warning dump if timeout happen in transfer
i2c: fix i2c-ismt.c printk format warning
i2c: i801: Add Device IDs for Intel Wellsburg PCH
i2c: add bcm2835 driver
i2c: ismt: Add Seth and Myself as maintainers
i2c: sis630: checkpatch cleanup
i2c: sis630: display unsigned hex
i2c: sis630: use hex to constants for SMBus commands
i2c: sis630: fix behavior after collision
i2c: sis630: clear sticky bits
i2c: sis630: Add SIS964 support
i2c: isch: Add module parameter for backbone clock rate if divider is unset
i2c: at91: fix unsed variable warning when building with !CONFIG_OF
i2c: Adding support for Intel iSMT SMBus 2.0 host controller
i2c: sh_mobile: don't send a stop condition by default inside transfers
i2c: sh_mobile: eliminate an open-coded "goto" loop
i2c: sh_mobile: fix timeout error handling
...
644 lines
18 KiB
C
644 lines
18 KiB
C
/*
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* Copyright (C) 2002 Motorola GSG-China
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
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* USA.
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*
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* Author:
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* Darius Augulis, Teltonika Inc.
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*
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* Desc.:
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* Implementation of I2C Adapter/Algorithm Driver
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* for I2C Bus integrated in Freescale i.MX/MXC processors
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*
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* Derived from Motorola GSG China I2C example driver
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*
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* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
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* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
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* Copyright (C) 2007 RightHand Technologies, Inc.
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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*/
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/** Includes *******************************************************************
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*******************************************************************************/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_i2c.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_data/i2c-imx.h>
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/** Defines ********************************************************************
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*******************************************************************************/
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/* This will be the driver name the kernel reports */
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#define DRIVER_NAME "imx-i2c"
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/* Default value */
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#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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/* IMX I2C registers */
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#define IMX_I2C_IADR 0x00 /* i2c slave address */
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#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
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#define IMX_I2C_I2CR 0x08 /* i2c control */
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#define IMX_I2C_I2SR 0x0C /* i2c status */
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#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
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/* Bits of IMX I2C registers */
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#define I2SR_RXAK 0x01
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#define I2SR_IIF 0x02
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#define I2SR_SRW 0x04
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#define I2SR_IAL 0x10
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#define I2SR_IBB 0x20
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#define I2SR_IAAS 0x40
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#define I2SR_ICF 0x80
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#define I2CR_RSTA 0x04
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#define I2CR_TXAK 0x08
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#define I2CR_MTX 0x10
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#define I2CR_MSTA 0x20
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#define I2CR_IIEN 0x40
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#define I2CR_IEN 0x80
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/** Variables ******************************************************************
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*******************************************************************************/
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/*
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* sorted list of clock divider, register value pairs
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* taken from table 26-5, p.26-9, Freescale i.MX
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* Integrated Portable System Processor Reference Manual
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* Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
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*
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* Duplicated divider values removed from list
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*/
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static u16 __initdata i2c_clk_div[50][2] = {
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
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{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
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{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
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{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
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{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
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{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
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{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
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{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
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{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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enum imx_i2c_type {
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IMX1_I2C,
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IMX21_I2C,
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};
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struct imx_i2c_struct {
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struct i2c_adapter adapter;
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struct clk *clk;
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void __iomem *base;
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wait_queue_head_t queue;
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unsigned long i2csr;
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unsigned int disable_delay;
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int stopped;
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unsigned int ifdr; /* IMX_I2C_IFDR */
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enum imx_i2c_type devtype;
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};
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static struct platform_device_id imx_i2c_devtype[] = {
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{
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.name = "imx1-i2c",
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.driver_data = IMX1_I2C,
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}, {
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.name = "imx21-i2c",
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.driver_data = IMX21_I2C,
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
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static const struct of_device_id i2c_imx_dt_ids[] = {
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{ .compatible = "fsl,imx1-i2c", .data = &imx_i2c_devtype[IMX1_I2C], },
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{ .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], },
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{ /* sentinel */ }
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};
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static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
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{
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return i2c_imx->devtype == IMX1_I2C;
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}
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/** Functions for IMX I2C adapter driver ***************************************
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*******************************************************************************/
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static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
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{
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unsigned long orig_jiffies = jiffies;
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unsigned int temp;
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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while (1) {
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temp = readb(i2c_imx->base + IMX_I2C_I2SR);
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if (for_busy && (temp & I2SR_IBB))
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break;
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if (!for_busy && !(temp & I2SR_IBB))
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break;
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> I2C bus is busy\n", __func__);
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return -ETIMEDOUT;
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}
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schedule();
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}
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return 0;
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}
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static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
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{
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wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
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if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
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dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
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return -ETIMEDOUT;
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}
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dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
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i2c_imx->i2csr = 0;
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return 0;
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}
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static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
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{
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if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
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dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
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return -EIO; /* No ACK */
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}
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dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
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return 0;
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}
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static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
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{
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unsigned int temp = 0;
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int result;
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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clk_prepare_enable(i2c_imx->clk);
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writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
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/* Enable I2C controller */
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writeb(0, i2c_imx->base + IMX_I2C_I2SR);
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writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
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/* Wait controller to be stable */
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udelay(50);
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/* Start I2C transaction */
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp |= I2CR_MSTA;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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result = i2c_imx_bus_busy(i2c_imx, 1);
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if (result)
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return result;
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i2c_imx->stopped = 0;
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temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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return result;
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}
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static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
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{
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unsigned int temp = 0;
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if (!i2c_imx->stopped) {
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/* Stop I2C transaction */
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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}
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if (is_imx1_i2c(i2c_imx)) {
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/*
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* This delay caused by an i.MXL hardware bug.
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* If no (or too short) delay, no "STOP" bit will be generated.
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*/
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udelay(i2c_imx->disable_delay);
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}
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if (!i2c_imx->stopped) {
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i2c_imx_bus_busy(i2c_imx, 0);
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i2c_imx->stopped = 1;
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}
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/* Disable I2C controller */
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writeb(0, i2c_imx->base + IMX_I2C_I2CR);
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clk_disable_unprepare(i2c_imx->clk);
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}
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static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
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unsigned int rate)
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{
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unsigned int i2c_clk_rate;
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unsigned int div;
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int i;
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/* Divider value calculation */
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i2c_clk_rate = clk_get_rate(i2c_imx->clk);
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div = (i2c_clk_rate + rate - 1) / rate;
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if (div < i2c_clk_div[0][0])
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i = 0;
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else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
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i = ARRAY_SIZE(i2c_clk_div) - 1;
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else
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for (i = 0; i2c_clk_div[i][0] < div; i++);
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/* Store divider value */
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i2c_imx->ifdr = i2c_clk_div[i][1];
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/*
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* There dummy delay is calculated.
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* It should be about one I2C clock period long.
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* This delay is used in I2C bus disable function
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* to fix chip hardware bug.
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*/
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i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
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+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
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/* dev_dbg() can't be used, because adapter is not yet registered */
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#ifdef CONFIG_I2C_DEBUG_BUS
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dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
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__func__, i2c_clk_rate, div);
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dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
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__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
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#endif
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}
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static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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{
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struct imx_i2c_struct *i2c_imx = dev_id;
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unsigned int temp;
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temp = readb(i2c_imx->base + IMX_I2C_I2SR);
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if (temp & I2SR_IIF) {
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/* save status register */
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i2c_imx->i2csr = temp;
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temp &= ~I2SR_IIF;
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writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
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wake_up(&i2c_imx->queue);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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{
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int i, result;
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dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
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__func__, msgs->addr << 1);
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/* write slave address */
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writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
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/* write data */
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for (i = 0; i < msgs->len; i++) {
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> write byte: B%d=0x%X\n",
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__func__, i, msgs->buf[i]);
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writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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}
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return 0;
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}
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static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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{
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int i, result;
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unsigned int temp;
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> write slave address: addr=0x%x\n",
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__func__, (msgs->addr << 1) | 0x01);
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/* write slave address */
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writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
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/* setup bus to read data */
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp &= ~I2CR_MTX;
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if (msgs->len - 1)
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temp &= ~I2CR_TXAK;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
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dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
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/* read data */
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for (i = 0; i < msgs->len; i++) {
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result = i2c_imx_trx_complete(i2c_imx);
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if (result)
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return result;
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if (i == (msgs->len - 1)) {
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/* It must generate STOP before read I2DR to prevent
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controller from generating another clock cycle */
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> clear MSTA\n", __func__);
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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i2c_imx_bus_busy(i2c_imx, 0);
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i2c_imx->stopped = 1;
|
|
} else if (i == (msgs->len - 2)) {
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
"<%s> set TXAK\n", __func__);
|
|
temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
|
temp |= I2CR_TXAK;
|
|
writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
|
|
}
|
|
msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
"<%s> read byte: B%d=0x%X\n",
|
|
__func__, i, msgs->buf[i]);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int i2c_imx_xfer(struct i2c_adapter *adapter,
|
|
struct i2c_msg *msgs, int num)
|
|
{
|
|
unsigned int i, temp;
|
|
int result;
|
|
struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
|
|
|
/* Start I2C transfer */
|
|
result = i2c_imx_start(i2c_imx);
|
|
if (result)
|
|
goto fail0;
|
|
|
|
/* read/write data */
|
|
for (i = 0; i < num; i++) {
|
|
if (i) {
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
"<%s> repeated start\n", __func__);
|
|
temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
|
temp |= I2CR_RSTA;
|
|
writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
|
|
result = i2c_imx_bus_busy(i2c_imx, 1);
|
|
if (result)
|
|
goto fail0;
|
|
}
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
"<%s> transfer message: %d\n", __func__, i);
|
|
/* write/read data */
|
|
#ifdef CONFIG_I2C_DEBUG_BUS
|
|
temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
|
|
"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
|
|
(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
|
|
(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
|
|
(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
|
|
temp = readb(i2c_imx->base + IMX_I2C_I2SR);
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
|
|
"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
|
|
(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
|
|
(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
|
|
(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
|
|
(temp & I2SR_RXAK ? 1 : 0));
|
|
#endif
|
|
if (msgs[i].flags & I2C_M_RD)
|
|
result = i2c_imx_read(i2c_imx, &msgs[i]);
|
|
else
|
|
result = i2c_imx_write(i2c_imx, &msgs[i]);
|
|
if (result)
|
|
goto fail0;
|
|
}
|
|
|
|
fail0:
|
|
/* Stop I2C transfer */
|
|
i2c_imx_stop(i2c_imx);
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
|
|
(result < 0) ? "error" : "success msg",
|
|
(result < 0) ? result : num);
|
|
return (result < 0) ? result : num;
|
|
}
|
|
|
|
static u32 i2c_imx_func(struct i2c_adapter *adapter)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
static struct i2c_algorithm i2c_imx_algo = {
|
|
.master_xfer = i2c_imx_xfer,
|
|
.functionality = i2c_imx_func,
|
|
};
|
|
|
|
static int __init i2c_imx_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
|
|
&pdev->dev);
|
|
struct imx_i2c_struct *i2c_imx;
|
|
struct resource *res;
|
|
struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
|
|
struct pinctrl *pinctrl;
|
|
void __iomem *base;
|
|
int irq, ret;
|
|
u32 bitrate;
|
|
|
|
dev_dbg(&pdev->dev, "<%s>\n", __func__);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "can't get device resources\n");
|
|
return -ENOENT;
|
|
}
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "can't get irq number\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
|
|
GFP_KERNEL);
|
|
if (!i2c_imx) {
|
|
dev_err(&pdev->dev, "can't allocate interface\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (of_id)
|
|
pdev->id_entry = of_id->data;
|
|
i2c_imx->devtype = pdev->id_entry->driver_data;
|
|
|
|
/* Setup i2c_imx driver structure */
|
|
strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
|
|
i2c_imx->adapter.owner = THIS_MODULE;
|
|
i2c_imx->adapter.algo = &i2c_imx_algo;
|
|
i2c_imx->adapter.dev.parent = &pdev->dev;
|
|
i2c_imx->adapter.nr = pdev->id;
|
|
i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
|
|
i2c_imx->base = base;
|
|
|
|
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
|
if (IS_ERR(pinctrl)) {
|
|
dev_err(&pdev->dev, "can't get/select pinctrl\n");
|
|
return PTR_ERR(pinctrl);
|
|
}
|
|
|
|
/* Get I2C clock */
|
|
i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(i2c_imx->clk)) {
|
|
dev_err(&pdev->dev, "can't get I2C clock\n");
|
|
return PTR_ERR(i2c_imx->clk);
|
|
}
|
|
|
|
/* Request IRQ */
|
|
ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
|
|
pdev->name, i2c_imx);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "can't claim irq %d\n", irq);
|
|
return ret;
|
|
}
|
|
|
|
/* Init queue */
|
|
init_waitqueue_head(&i2c_imx->queue);
|
|
|
|
/* Set up adapter data */
|
|
i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
|
|
|
|
/* Set up clock divider */
|
|
bitrate = IMX_I2C_BIT_RATE;
|
|
ret = of_property_read_u32(pdev->dev.of_node,
|
|
"clock-frequency", &bitrate);
|
|
if (ret < 0 && pdata && pdata->bitrate)
|
|
bitrate = pdata->bitrate;
|
|
i2c_imx_set_clk(i2c_imx, bitrate);
|
|
|
|
/* Set up chip registers to defaults */
|
|
writeb(0, i2c_imx->base + IMX_I2C_I2CR);
|
|
writeb(0, i2c_imx->base + IMX_I2C_I2SR);
|
|
|
|
/* Add I2C adapter */
|
|
ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "registration failed\n");
|
|
return ret;
|
|
}
|
|
|
|
of_i2c_register_devices(&i2c_imx->adapter);
|
|
|
|
/* Set up platform driver data */
|
|
platform_set_drvdata(pdev, i2c_imx);
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
|
|
dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
|
|
res->start, res->end);
|
|
dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
|
|
resource_size(res), res->start);
|
|
dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
|
|
i2c_imx->adapter.name);
|
|
dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
|
|
|
|
return 0; /* Return OK */
|
|
}
|
|
|
|
static int __exit i2c_imx_remove(struct platform_device *pdev)
|
|
{
|
|
struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
|
|
|
|
/* remove adapter */
|
|
dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
|
|
i2c_del_adapter(&i2c_imx->adapter);
|
|
|
|
/* setup chip registers to defaults */
|
|
writeb(0, i2c_imx->base + IMX_I2C_IADR);
|
|
writeb(0, i2c_imx->base + IMX_I2C_IFDR);
|
|
writeb(0, i2c_imx->base + IMX_I2C_I2CR);
|
|
writeb(0, i2c_imx->base + IMX_I2C_I2SR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver i2c_imx_driver = {
|
|
.remove = __exit_p(i2c_imx_remove),
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = i2c_imx_dt_ids,
|
|
},
|
|
.id_table = imx_i2c_devtype,
|
|
};
|
|
|
|
static int __init i2c_adap_imx_init(void)
|
|
{
|
|
return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
|
|
}
|
|
subsys_initcall(i2c_adap_imx_init);
|
|
|
|
static void __exit i2c_adap_imx_exit(void)
|
|
{
|
|
platform_driver_unregister(&i2c_imx_driver);
|
|
}
|
|
module_exit(i2c_adap_imx_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Darius Augulis");
|
|
MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|