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1e820da3c9
New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
181 lines
4.0 KiB
C
181 lines
4.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#ifndef _ASM_IRQFLAGS_H
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#define _ASM_IRQFLAGS_H
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/stringify.h>
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#include <asm/compiler.h>
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#include <asm/hazards.h>
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#if defined(CONFIG_CPU_MIPSR2) || defined (CONFIG_CPU_MIPSR6)
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static inline void arch_local_irq_disable(void)
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{
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" di \n"
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" " __stringify(__irq_disable_hazard) " \n"
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" .set pop \n"
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: /* no outputs */
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: /* no inputs */
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: "memory");
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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unsigned long flags;
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asm __volatile__(
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" .set push \n"
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" .set reorder \n"
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" .set noat \n"
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#if defined(CONFIG_CPU_LOONGSON3)
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" mfc0 %[flags], $12 \n"
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" di \n"
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#else
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" di %[flags] \n"
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#endif
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" andi %[flags], 1 \n"
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" " __stringify(__irq_disable_hazard) " \n"
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" .set pop \n"
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: [flags] "=r" (flags)
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: /* no inputs */
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: "memory");
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return flags;
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}
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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unsigned long __tmp1;
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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#if defined(CONFIG_IRQ_MIPS_CPU)
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/*
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* Slow, but doesn't suffer from a relatively unlikely race
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* condition we're having since days 1.
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*/
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" beqz %[flags], 1f \n"
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" di \n"
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" ei \n"
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"1: \n"
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#else
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/*
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* Fast, dangerous. Life is fun, life is good.
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*/
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" mfc0 $1, $12 \n"
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" ins $1, %[flags], 0, 1 \n"
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" mtc0 $1, $12 \n"
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#endif
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" " __stringify(__irq_disable_hazard) " \n"
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" .set pop \n"
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: [flags] "=r" (__tmp1)
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: "0" (flags)
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: "memory");
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}
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#else
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/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
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void arch_local_irq_disable(void);
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unsigned long arch_local_irq_save(void);
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void arch_local_irq_restore(unsigned long flags);
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#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
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static inline void arch_local_irq_enable(void)
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{
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__asm__ __volatile__(
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" .set push \n"
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" .set reorder \n"
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" .set noat \n"
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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" ei \n"
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#else
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" mfc0 $1,$12 \n"
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" ori $1,0x1f \n"
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" xori $1,0x1e \n"
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" mtc0 $1,$12 \n"
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#endif
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" " __stringify(__irq_enable_hazard) " \n"
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" .set pop \n"
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: /* no outputs */
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: /* no inputs */
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: "memory");
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}
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static inline unsigned long arch_local_save_flags(void)
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{
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unsigned long flags;
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asm __volatile__(
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" .set push \n"
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" .set reorder \n"
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" mfc0 %[flags], $12 \n"
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" .set pop \n"
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: [flags] "=r" (flags));
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return flags;
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}
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & 1);
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}
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#endif /* #ifndef __ASSEMBLY__ */
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/*
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* Do the CPU's IRQ-state tracing from assembly code.
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*/
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#ifdef CONFIG_TRACE_IRQFLAGS
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/* Reload some registers clobbered by trace_hardirqs_on */
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#ifdef CONFIG_64BIT
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# define TRACE_IRQS_RELOAD_REGS \
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LONG_L $11, PT_R11(sp); \
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LONG_L $10, PT_R10(sp); \
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LONG_L $9, PT_R9(sp); \
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LONG_L $8, PT_R8(sp); \
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LONG_L $7, PT_R7(sp); \
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LONG_L $6, PT_R6(sp); \
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LONG_L $5, PT_R5(sp); \
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LONG_L $4, PT_R4(sp); \
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LONG_L $2, PT_R2(sp)
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#else
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# define TRACE_IRQS_RELOAD_REGS \
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LONG_L $7, PT_R7(sp); \
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LONG_L $6, PT_R6(sp); \
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LONG_L $5, PT_R5(sp); \
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LONG_L $4, PT_R4(sp); \
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LONG_L $2, PT_R2(sp)
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#endif
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# define TRACE_IRQS_ON \
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CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
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jal trace_hardirqs_on
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# define TRACE_IRQS_ON_RELOAD \
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TRACE_IRQS_ON; \
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TRACE_IRQS_RELOAD_REGS
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# define TRACE_IRQS_OFF \
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jal trace_hardirqs_off
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#else
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# define TRACE_IRQS_ON
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# define TRACE_IRQS_ON_RELOAD
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# define TRACE_IRQS_OFF
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#endif
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#endif /* _ASM_IRQFLAGS_H */
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