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Split the DP PHY register definitions to separate headers, removing them from the global one. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-4-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
63 lines
2.1 KiB
C
63 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_DP_PHY_H_
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#define QCOM_PHY_QMP_DP_PHY_H_
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/* QMP PHY - DP PHY registers */
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#define QSERDES_DP_PHY_REVISION_ID0 0x000
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#define QSERDES_DP_PHY_REVISION_ID1 0x004
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#define QSERDES_DP_PHY_REVISION_ID2 0x008
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#define QSERDES_DP_PHY_REVISION_ID3 0x00c
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#define QSERDES_DP_PHY_CFG 0x010
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#define QSERDES_DP_PHY_CFG_1 0x014
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#define QSERDES_DP_PHY_PD_CTL 0x018
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#define QSERDES_DP_PHY_MODE 0x01c
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#define QSERDES_DP_PHY_AUX_CFG0 0x020
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#define QSERDES_DP_PHY_AUX_CFG1 0x024
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#define QSERDES_DP_PHY_AUX_CFG2 0x028
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#define QSERDES_DP_PHY_AUX_CFG3 0x02c
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#define QSERDES_DP_PHY_AUX_CFG4 0x030
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#define QSERDES_DP_PHY_AUX_CFG5 0x034
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#define QSERDES_DP_PHY_AUX_CFG6 0x038
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#define QSERDES_DP_PHY_AUX_CFG7 0x03c
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#define QSERDES_DP_PHY_AUX_CFG8 0x040
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#define QSERDES_DP_PHY_AUX_CFG9 0x044
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/* QSERDES COM_BIAS_EN_CLKBUFLR_EN bits */
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# define QSERDES_V3_COM_BIAS_EN 0x0001
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# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
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# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
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# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
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# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
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# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
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# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
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/* QPHY_TX_TX_EMP_POST1_LVL bits */
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# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
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# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
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/* QPHY_TX_TX_DRV_LVL bits */
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# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
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# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
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/* QSERDES_DP_PHY_PD_CTL bits */
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# define DP_PHY_PD_CTL_PWRDN 0x001
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# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
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# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
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# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
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# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
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# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
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# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
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/* QPHY_DP_PHY_AUX_INTERRUPT_STATUS bits */
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# define PHY_AUX_STOP_ERR_MASK 0x01
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# define PHY_AUX_DEC_ERR_MASK 0x02
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# define PHY_AUX_SYNC_ERR_MASK 0x04
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# define PHY_AUX_ALIGN_ERR_MASK 0x08
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# define PHY_AUX_REQ_ERR_MASK 0x10
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#endif
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