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b9920fdd5a
PJ4 is a v7 core that incorporates a iWMMXt coprocessor. However, GCC
does not support this combination (its iWMMXt configuration always
implies v5te), and so there is no v6/v7 user space that actually makes
use of this, beyond generic support for things like setjmp() that
preserve/restore the iWMMXt register file using generic LDC/STC
instructions emitted in assembler. As [0] appears to imply, this logic
is triggered for the init process at boot, and so most user threads will
have a iWMMXt register context associated with it, even though it is
never used.
At this point, it is highly unlikely that such GCC support will ever
materialize (and Clang does not implement support for iWMMXt to begin
with).
This means that advertising iWMMXt support on these cores results in
context switch overhead without any associated benefit, and so it is
better to simply ignore the iWMMXt unit on these systems. So rip out the
support. Doing so also fixes the issue reported in [0] related to UNDEF
handling of co-processor #0/#1 instructions issued from user space
running in Thumb2 mode.
The PJ4 cores are used in four platforms: Armada 370/xp, Dove (Cubox,
d2plug), MMP2 (xo-1.75) and Berlin (Google TV). Out of these, only the
first is still widely used, but that one actually doesn't have iWMMXt
but instead has only VFPV3-D16, and so it is not impacted by this
change.
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218427 [0]
Fixes: 8bcba70cb5 ("ARM: entry: Disregard Thumb undef exception ...")
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
357 lines
7.7 KiB
ArmAsm
357 lines
7.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/kernel/iwmmxt.S
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*
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* XScale iWMMXt (Concan) context switching and handling
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*
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* Initial code:
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* Copyright (c) 2003, Intel Corporation
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*
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* Full lazy switching support, optimizations and more, by Nicolas Pitre
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* Copyright (c) 2003-2004, MontaVista Software, Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include "iwmmxt.h"
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#define MMX_WR0 (0x00)
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#define MMX_WR1 (0x08)
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#define MMX_WR2 (0x10)
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#define MMX_WR3 (0x18)
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#define MMX_WR4 (0x20)
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#define MMX_WR5 (0x28)
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#define MMX_WR6 (0x30)
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#define MMX_WR7 (0x38)
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#define MMX_WR8 (0x40)
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#define MMX_WR9 (0x48)
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#define MMX_WR10 (0x50)
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#define MMX_WR11 (0x58)
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#define MMX_WR12 (0x60)
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#define MMX_WR13 (0x68)
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#define MMX_WR14 (0x70)
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#define MMX_WR15 (0x78)
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#define MMX_WCSSF (0x80)
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#define MMX_WCASF (0x84)
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#define MMX_WCGR0 (0x88)
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#define MMX_WCGR1 (0x8C)
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#define MMX_WCGR2 (0x90)
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#define MMX_WCGR3 (0x94)
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#define MMX_SIZE (0x98)
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.text
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.arm
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ENTRY(iwmmxt_undef_handler)
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push {r9, r10, lr}
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get_thread_info r10
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mov r9, pc
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b iwmmxt_task_enable
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mov r0, #0
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pop {r9, r10, pc}
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ENDPROC(iwmmxt_undef_handler)
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/*
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* Lazy switching of Concan coprocessor context
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*
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* r0 = struct pt_regs pointer
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* r10 = struct thread_info pointer
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* r9 = ret_from_exception
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* lr = undefined instr exit
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*
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* called from prefetch exception handler with interrupts enabled
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*/
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ENTRY(iwmmxt_task_enable)
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inc_preempt_count r10, r3
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mrc p15, 0, r2, c15, c1, 0
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@ CP0 and CP1 accessible?
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tst r2, #0x3
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bne 4f @ if so no business here
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@ enable access to CP0 and CP1
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orr r2, r2, #0x3
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mcr p15, 0, r2, c15, c1, 0
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ldr r3, =concan_owner
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ldr r2, [r0, #S_PC] @ current task pc value
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ldr r1, [r3] @ get current Concan owner
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sub r2, r2, #4 @ adjust pc back
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str r2, [r0, #S_PC]
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add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
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str r0, [r3] @ this task now owns Concan regs
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mrc p15, 0, r2, c2, c0, 0
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mov r2, r2 @ cpwait
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bl concan_save
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#ifdef CONFIG_PREEMPT_COUNT
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get_thread_info r10
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#endif
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4: dec_preempt_count r10, r3
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ret r9 @ normal exit from exception
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concan_save:
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teq r1, #0 @ test for last ownership
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beq concan_load @ no owner, skip save
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tmrc r2, wCon
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@ CUP? wCx
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tst r2, #0x1
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beq 1f
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concan_dump:
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wstrw wCSSF, r1, MMX_WCSSF
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wstrw wCASF, r1, MMX_WCASF
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wstrw wCGR0, r1, MMX_WCGR0
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wstrw wCGR1, r1, MMX_WCGR1
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wstrw wCGR2, r1, MMX_WCGR2
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wstrw wCGR3, r1, MMX_WCGR3
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1: @ MUP? wRn
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tst r2, #0x2
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beq 2f
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wstrd wR0, r1, MMX_WR0
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wstrd wR1, r1, MMX_WR1
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wstrd wR2, r1, MMX_WR2
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wstrd wR3, r1, MMX_WR3
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wstrd wR4, r1, MMX_WR4
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wstrd wR5, r1, MMX_WR5
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wstrd wR6, r1, MMX_WR6
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wstrd wR7, r1, MMX_WR7
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wstrd wR8, r1, MMX_WR8
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wstrd wR9, r1, MMX_WR9
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wstrd wR10, r1, MMX_WR10
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wstrd wR11, r1, MMX_WR11
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wstrd wR12, r1, MMX_WR12
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wstrd wR13, r1, MMX_WR13
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wstrd wR14, r1, MMX_WR14
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wstrd wR15, r1, MMX_WR15
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2: teq r0, #0 @ anything to load?
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reteq lr @ if not, return
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concan_load:
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@ Load wRn
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wldrd wR0, r0, MMX_WR0
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wldrd wR1, r0, MMX_WR1
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wldrd wR2, r0, MMX_WR2
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wldrd wR3, r0, MMX_WR3
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wldrd wR4, r0, MMX_WR4
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wldrd wR5, r0, MMX_WR5
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wldrd wR6, r0, MMX_WR6
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wldrd wR7, r0, MMX_WR7
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wldrd wR8, r0, MMX_WR8
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wldrd wR9, r0, MMX_WR9
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wldrd wR10, r0, MMX_WR10
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wldrd wR11, r0, MMX_WR11
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wldrd wR12, r0, MMX_WR12
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wldrd wR13, r0, MMX_WR13
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wldrd wR14, r0, MMX_WR14
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wldrd wR15, r0, MMX_WR15
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@ Load wCx
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wldrw wCSSF, r0, MMX_WCSSF
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wldrw wCASF, r0, MMX_WCASF
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wldrw wCGR0, r0, MMX_WCGR0
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wldrw wCGR1, r0, MMX_WCGR1
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wldrw wCGR2, r0, MMX_WCGR2
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wldrw wCGR3, r0, MMX_WCGR3
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@ clear CUP/MUP (only if r1 != 0)
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teq r1, #0
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mov r2, #0
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reteq lr
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tmcr wCon, r2
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ret lr
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ENDPROC(iwmmxt_task_enable)
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/*
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* Back up Concan regs to save area and disable access to them
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* (mainly for gdb or sleep mode usage)
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*
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* r0 = struct thread_info pointer of target task or NULL for any
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*/
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ENTRY(iwmmxt_task_disable)
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stmfd sp!, {r4, lr}
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mrs ip, cpsr
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orr r2, ip, #PSR_I_BIT @ disable interrupts
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msr cpsr_c, r2
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ldr r3, =concan_owner
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add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
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ldr r1, [r3] @ get current Concan owner
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teq r1, #0 @ any current owner?
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beq 1f @ no: quit
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teq r0, #0 @ any owner?
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teqne r1, r2 @ or specified one?
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bne 1f @ no: quit
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@ enable access to CP0 and CP1
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mrc p15, 0, r4, c15, c1, 0
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orr r4, r4, #0x3
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mcr p15, 0, r4, c15, c1, 0
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mov r0, #0 @ nothing to load
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str r0, [r3] @ no more current owner
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mrc p15, 0, r2, c2, c0, 0
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mov r2, r2 @ cpwait
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bl concan_save
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@ disable access to CP0 and CP1
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bic r4, r4, #0x3
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mcr p15, 0, r4, c15, c1, 0
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mrc p15, 0, r2, c2, c0, 0
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mov r2, r2 @ cpwait
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1: msr cpsr_c, ip @ restore interrupt mode
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ldmfd sp!, {r4, pc}
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ENDPROC(iwmmxt_task_disable)
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/*
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* Copy Concan state to given memory address
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*
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* r0 = struct thread_info pointer of target task
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* r1 = memory address where to store Concan state
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*
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* this is called mainly in the creation of signal stack frames
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*/
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ENTRY(iwmmxt_task_copy)
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mrs ip, cpsr
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orr r2, ip, #PSR_I_BIT @ disable interrupts
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msr cpsr_c, r2
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ldr r3, =concan_owner
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add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
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ldr r3, [r3] @ get current Concan owner
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teq r2, r3 @ does this task own it...
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beq 1f
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@ current Concan values are in the task save area
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msr cpsr_c, ip @ restore interrupt mode
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mov r0, r1
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mov r1, r2
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mov r2, #MMX_SIZE
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b memcpy
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1: @ this task owns Concan regs -- grab a copy from there
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mov r0, #0 @ nothing to load
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mov r2, #3 @ save all regs
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mov r3, lr @ preserve return address
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bl concan_dump
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msr cpsr_c, ip @ restore interrupt mode
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ret r3
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ENDPROC(iwmmxt_task_copy)
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/*
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* Restore Concan state from given memory address
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*
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* r0 = struct thread_info pointer of target task
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* r1 = memory address where to get Concan state from
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*
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* this is used to restore Concan state when unwinding a signal stack frame
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*/
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ENTRY(iwmmxt_task_restore)
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mrs ip, cpsr
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orr r2, ip, #PSR_I_BIT @ disable interrupts
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msr cpsr_c, r2
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ldr r3, =concan_owner
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add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
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ldr r3, [r3] @ get current Concan owner
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bic r2, r2, #0x7 @ 64-bit alignment
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teq r2, r3 @ does this task own it...
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beq 1f
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@ this task doesn't own Concan regs -- use its save area
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msr cpsr_c, ip @ restore interrupt mode
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mov r0, r2
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mov r2, #MMX_SIZE
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b memcpy
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1: @ this task owns Concan regs -- load them directly
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mov r0, r1
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mov r1, #0 @ don't clear CUP/MUP
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mov r3, lr @ preserve return address
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bl concan_load
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msr cpsr_c, ip @ restore interrupt mode
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ret r3
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ENDPROC(iwmmxt_task_restore)
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/*
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* Concan handling on task switch
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*
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* r0 = next thread_info pointer
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*
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* Called only from the iwmmxt notifier with task preemption disabled.
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*/
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ENTRY(iwmmxt_task_switch)
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mrc p15, 0, r1, c15, c1, 0
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@ CP0 and CP1 accessible?
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tst r1, #0x3
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bne 1f @ yes: block them for next task
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ldr r2, =concan_owner
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add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
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ldr r2, [r2] @ get current Concan owner
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teq r2, r3 @ next task owns it?
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retne lr @ no: leave Concan disabled
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1: @ flip Concan access
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eor r1, r1, #0x3
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mcr p15, 0, r1, c15, c1, 0
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mrc p15, 0, r1, c2, c0, 0
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sub pc, lr, r1, lsr #32 @ cpwait and return
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ENDPROC(iwmmxt_task_switch)
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/*
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* Remove Concan ownership of given task
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*
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* r0 = struct thread_info pointer
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*/
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ENTRY(iwmmxt_task_release)
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mrs r2, cpsr
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orr ip, r2, #PSR_I_BIT @ disable interrupts
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msr cpsr_c, ip
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ldr r3, =concan_owner
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add r0, r0, #TI_IWMMXT_STATE @ get task Concan save area
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ldr r1, [r3] @ get current Concan owner
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eors r0, r0, r1 @ if equal...
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streq r0, [r3] @ then clear ownership
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msr cpsr_c, r2 @ restore interrupts
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ret lr
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ENDPROC(iwmmxt_task_release)
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.data
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.align 2
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concan_owner:
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.word 0
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