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1d3928a3e6
Currently, the common R-Car bias handling supports pin controllers with
either:
1. Separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD)
registers, for controlling both pin pull-up and pin pull-down,
2. A single pin Pull-Up control register (PUPR), for controlling pin
pull-up.
Add support for a variant of #2, where some bits in the single pin
Pull-Up control register (PUPR) control pin pull-down instead of pin
pull-up. This is the case for the "ASEBRK#/ACK" pin on R-Car M2-W,
M2-N, and E2, and the "ACK" pin on RZ/G1M, RZ/G1N, RZ/G1E, and RZ/G1C.
To describe such a register, SoC-specific drivers need to provide two
instances of pinmux_bias_reg: a first one with the puen field filled in,
listing pins with pull-up functionality, and a second one with the pud
field filled in, listing pins with pull-down functionality.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-6-geert+renesas@glider.be
793 lines
26 KiB
C
793 lines
26 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* SuperH Pin Function Controller Support
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*
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* Copyright (c) 2008 Magnus Damm
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*/
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#ifndef __SH_PFC_H
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#define __SH_PFC_H
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#include <linux/bug.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/spinlock.h>
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#include <linux/stringify.h>
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enum {
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PINMUX_TYPE_NONE,
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PINMUX_TYPE_FUNCTION,
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PINMUX_TYPE_GPIO,
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PINMUX_TYPE_OUTPUT,
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PINMUX_TYPE_INPUT,
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};
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#define SH_PFC_PIN_NONE U16_MAX
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#define SH_PFC_PIN_CFG_INPUT (1 << 0)
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#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
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#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
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#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
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#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
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SH_PFC_PIN_CFG_PULL_DOWN)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
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#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
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#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
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#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
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SH_PFC_PIN_VOLTAGE_18_33)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
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SH_PFC_PIN_VOLTAGE_25_33)
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#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
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struct sh_pfc_pin {
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const char *name;
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unsigned int configs;
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u16 pin;
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u16 enum_id;
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};
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#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
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{ \
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.name = #alias, \
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.pins = n##_pins, \
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.mux = n##_mux, \
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.nr_pins = ARRAY_SIZE(n##_pins) + \
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BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
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}
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#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
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struct sh_pfc_pin_group {
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const char *name;
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const unsigned int *pins;
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const unsigned int *mux;
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unsigned int nr_pins;
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};
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/*
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* Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
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* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
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* in this case. It accepts an optional 'version' argument used when the
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* same group can appear on a different set of pins.
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*/
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#define VIN_DATA_PIN_GROUP(n, s, ...) \
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{ \
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.name = #n#s#__VA_ARGS__, \
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.pins = n##__VA_ARGS__##_pins.data##s, \
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.mux = n##__VA_ARGS__##_mux.data##s, \
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.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
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}
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union vin_data12 {
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unsigned int data12[12];
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unsigned int data10[10];
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unsigned int data8[8];
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};
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union vin_data16 {
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unsigned int data16[16];
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unsigned int data12[12];
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unsigned int data10[10];
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unsigned int data8[8];
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};
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union vin_data {
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unsigned int data24[24];
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unsigned int data20[20];
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unsigned int data16[16];
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unsigned int data12[12];
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unsigned int data10[10];
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unsigned int data8[8];
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unsigned int data4[4];
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};
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#define SH_PFC_FUNCTION(n) \
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{ \
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.name = #n, \
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.groups = n##_groups, \
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.nr_groups = ARRAY_SIZE(n##_groups), \
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}
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struct sh_pfc_function {
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const char *name;
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const char * const *groups;
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unsigned int nr_groups;
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};
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struct pinmux_func {
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u16 enum_id;
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const char *name;
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};
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struct pinmux_cfg_reg {
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u32 reg;
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u8 reg_width, field_width;
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#ifdef DEBUG
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u16 nr_enum_ids; /* for variable width regs only */
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#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
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#else
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#define SET_NR_ENUM_IDS(n)
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#endif
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const u16 *enum_ids;
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const u8 *var_field_width;
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};
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#define GROUP(...) __VA_ARGS__
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/*
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* Describe a config register consisting of several fields of the same width
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* - name: Register name (unused, for documentation purposes only)
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* - r: Physical register address
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* - r_width: Width of the register (in bits)
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* - f_width: Width of the fixed-width register fields (in bits)
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* - ids: For each register field (from left to right, i.e. MSB to LSB),
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* 2^f_width enum IDs must be specified, one for each possible
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* combination of the register field bit values, all wrapped using
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* the GROUP() macro.
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*/
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#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
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.reg = r, .reg_width = r_width, \
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.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
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BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
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(r_width / f_width) * (1 << f_width)), \
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.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
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{ ids }
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/*
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* Describe a config register consisting of several fields of different widths
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* - name: Register name (unused, for documentation purposes only)
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* - r: Physical register address
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* - r_width: Width of the register (in bits)
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* - f_widths: List of widths of the register fields (in bits), from left
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* to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
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* - ids: For each register field (from left to right, i.e. MSB to LSB),
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* 2^f_widths[i] enum IDs must be specified, one for each possible
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* combination of the register field bit values, all wrapped using
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* the GROUP() macro.
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*/
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#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
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.reg = r, .reg_width = r_width, \
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.var_field_width = (const u8 []) { f_widths, 0 }, \
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SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
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.enum_ids = (const u16 []) { ids }
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struct pinmux_drive_reg_field {
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u16 pin;
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u8 offset;
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u8 size;
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};
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struct pinmux_drive_reg {
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u32 reg;
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const struct pinmux_drive_reg_field fields[8];
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};
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#define PINMUX_DRIVE_REG(name, r) \
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.reg = r, \
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.fields =
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struct pinmux_bias_reg { /* At least one of puen/pud must exist */
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u32 puen; /* Pull-enable or pull-up control register */
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u32 pud; /* Pull-up/down or pull-down control register */
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const u16 pins[32];
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};
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#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
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.puen = r1, \
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.pud = r2, \
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.pins =
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struct pinmux_ioctrl_reg {
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u32 reg;
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};
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struct pinmux_data_reg {
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u32 reg;
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u8 reg_width;
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const u16 *enum_ids;
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};
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/*
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* Describe a data register
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* - name: Register name (unused, for documentation purposes only)
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* - r: Physical register address
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* - r_width: Width of the register (in bits)
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* - ids: For each register bit (from left to right, i.e. MSB to LSB), one
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* enum ID must be specified, all wrapped using the GROUP() macro.
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*/
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#define PINMUX_DATA_REG(name, r, r_width, ids) \
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.reg = r, .reg_width = r_width + \
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BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
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r_width), \
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.enum_ids = (const u16 [r_width]) { ids }
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struct pinmux_irq {
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const short *gpios;
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};
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/*
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* Describe the mapping from GPIOs to a single IRQ
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* - ids...: List of GPIOs that are mapped to the same IRQ
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*/
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#define PINMUX_IRQ(ids...) \
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{ .gpios = (const short []) { ids, -1 } }
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struct pinmux_range {
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u16 begin;
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u16 end;
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u16 force;
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};
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struct sh_pfc_window {
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phys_addr_t phys;
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void __iomem *virt;
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unsigned long size;
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};
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struct sh_pfc_pin_range;
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struct sh_pfc {
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struct device *dev;
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const struct sh_pfc_soc_info *info;
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spinlock_t lock;
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unsigned int num_windows;
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struct sh_pfc_window *windows;
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unsigned int num_irqs;
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unsigned int *irqs;
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struct sh_pfc_pin_range *ranges;
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unsigned int nr_ranges;
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unsigned int nr_gpio_pins;
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struct sh_pfc_chip *gpio;
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u32 *saved_regs;
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};
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struct sh_pfc_soc_operations {
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int (*init)(struct sh_pfc *pfc);
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unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
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void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
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unsigned int bias);
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int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
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void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin);
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};
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struct sh_pfc_soc_info {
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const char *name;
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const struct sh_pfc_soc_operations *ops;
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#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
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struct pinmux_range input;
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struct pinmux_range output;
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const struct pinmux_irq *gpio_irq;
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unsigned int gpio_irq_size;
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#endif
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struct pinmux_range function;
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const struct sh_pfc_pin *pins;
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unsigned int nr_pins;
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const struct sh_pfc_pin_group *groups;
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unsigned int nr_groups;
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const struct sh_pfc_function *functions;
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unsigned int nr_functions;
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#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
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const struct pinmux_func *func_gpios;
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unsigned int nr_func_gpios;
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#endif
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const struct pinmux_cfg_reg *cfg_regs;
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const struct pinmux_drive_reg *drive_regs;
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const struct pinmux_bias_reg *bias_regs;
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const struct pinmux_ioctrl_reg *ioctrl_regs;
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const struct pinmux_data_reg *data_regs;
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const u16 *pinmux_data;
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unsigned int pinmux_data_size;
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u32 unlock_reg; /* can be literal address or mask */
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};
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extern const struct sh_pfc_soc_info emev2_pinmux_info;
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extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
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extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
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extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
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extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
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extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
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extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
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extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
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extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
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extern const struct sh_pfc_soc_info sh7203_pinmux_info;
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extern const struct sh_pfc_soc_info sh7264_pinmux_info;
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extern const struct sh_pfc_soc_info sh7269_pinmux_info;
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extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
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extern const struct sh_pfc_soc_info sh7720_pinmux_info;
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extern const struct sh_pfc_soc_info sh7722_pinmux_info;
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extern const struct sh_pfc_soc_info sh7723_pinmux_info;
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extern const struct sh_pfc_soc_info sh7724_pinmux_info;
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extern const struct sh_pfc_soc_info sh7734_pinmux_info;
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extern const struct sh_pfc_soc_info sh7757_pinmux_info;
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extern const struct sh_pfc_soc_info sh7785_pinmux_info;
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extern const struct sh_pfc_soc_info sh7786_pinmux_info;
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extern const struct sh_pfc_soc_info shx3_pinmux_info;
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/* -----------------------------------------------------------------------------
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* Helper macros to create pin and port lists
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*/
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/*
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* sh_pfc_soc_info pinmux_data array macros
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*/
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/*
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* Describe generic pinmux data
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* - data_or_mark: *_DATA or *_MARK enum ID
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* - ids...: List of enum IDs to associate with data_or_mark
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*/
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#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
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/*
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* Describe a pinmux configuration without GPIO function that needs
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* configuration in a Peripheral Function Select Register (IPSR)
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* - ipsr: IPSR field (unused, for documentation purposes only)
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* - fn: Function name, referring to a field in the IPSR
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*/
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#define PINMUX_IPSR_NOGP(ipsr, fn) \
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PINMUX_DATA(fn##_MARK, FN_##fn)
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/*
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* Describe a pinmux configuration with GPIO function that needs configuration
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* in both a Peripheral Function Select Register (IPSR) and in a
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* GPIO/Peripheral Function Select Register (GPSR)
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* - ipsr: IPSR field
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* - fn: Function name, also referring to the IPSR field
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*/
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#define PINMUX_IPSR_GPSR(ipsr, fn) \
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PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
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/*
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* Describe a pinmux configuration without GPIO function that needs
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* configuration in a Peripheral Function Select Register (IPSR), and where the
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* pinmux function has a representation in a Module Select Register (MOD_SEL).
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* - ipsr: IPSR field (unused, for documentation purposes only)
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* - fn: Function name, also referring to the IPSR field
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* - msel: Module selector
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*/
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#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
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PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
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/*
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* Describe a pinmux configuration with GPIO function where the pinmux function
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* has no representation in a Peripheral Function Select Register (IPSR), but
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* instead solely depends on a group selection.
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* - gpsr: GPSR field
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* - fn: Function name, also referring to the GPSR field
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* - gsel: Group selector
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*/
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#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
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PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
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/*
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* Describe a pinmux configuration with GPIO function that needs configuration
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* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
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* Function Select Register (GPSR), and where the pinmux function has a
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* representation in a Module Select Register (MOD_SEL).
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* - ipsr: IPSR field
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* - fn: Function name, also referring to the IPSR field
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* - msel: Module selector
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*/
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#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
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PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
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/*
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* Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
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* an additional select register that controls physical multiplexing
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* with another pin.
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* - ipsr: IPSR field
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* - fn: Function name, also referring to the IPSR field
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* - psel: Physical multiplexing selector
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* - msel: Module selector
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*/
|
|
#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
|
|
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
|
|
|
|
/*
|
|
* Describe a pinmux configuration in which a pin is physically multiplexed
|
|
* with other pins.
|
|
* - ipsr: IPSR field
|
|
* - fn: Function name
|
|
* - psel: Physical multiplexing selector
|
|
*/
|
|
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
|
|
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
|
|
|
|
/*
|
|
* Describe a pinmux configuration for a single-function pin with GPIO
|
|
* capability.
|
|
* - fn: Function name
|
|
*/
|
|
#define PINMUX_SINGLE(fn) \
|
|
PINMUX_DATA(fn##_MARK, FN_##fn)
|
|
|
|
/*
|
|
* GP port style (32 ports banks)
|
|
*/
|
|
|
|
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
|
|
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
|
|
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
|
|
#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_2(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
|
|
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
|
|
#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_7(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_6(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg)
|
|
#define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_7(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
|
|
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
|
|
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_9(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
|
|
#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
|
|
#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_11(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
|
|
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
|
|
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
|
|
#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_15(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
|
|
#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
|
|
#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_17(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
|
|
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
|
|
#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_20(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
|
|
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
|
|
#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_22(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
|
|
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_23(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
|
|
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
|
|
#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_25(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
|
|
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
|
|
#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_27(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
|
|
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
|
|
#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_29(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
|
|
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
|
|
#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
|
|
PORT_GP_CFG_31(bank, fn, sfx, cfg), \
|
|
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
|
|
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
|
|
|
|
#define PORT_GP_32_REV(bank, fn, sfx) \
|
|
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
|
|
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
|
|
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
|
|
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
|
|
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
|
|
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
|
|
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
|
|
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
|
|
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
|
|
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
|
|
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
|
|
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
|
|
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
|
|
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
|
|
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
|
|
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
|
|
|
|
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
|
|
#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
|
|
#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
|
|
|
|
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
|
|
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
|
|
{ \
|
|
.pin = (bank * 32) + _pin, \
|
|
.name = __stringify(_name), \
|
|
.enum_id = _name##_DATA, \
|
|
.configs = cfg, \
|
|
}
|
|
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
|
|
|
|
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
|
|
#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
|
|
#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
|
|
|
|
/*
|
|
* GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
|
|
*
|
|
* The largest GP pin index is obtained by taking the size of a union,
|
|
* containing one array per GP pin, sized by the corresponding pin index.
|
|
* As the fields in the CPU_ALL_GP() macro definition are separated by commas,
|
|
* while the members of a union must be terminated by semicolons, the commas
|
|
* are absorbed by wrapping them inside dummy attributes.
|
|
*/
|
|
#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
|
|
deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
|
|
#define GP_ASSIGN_LAST() \
|
|
GP_LAST = sizeof(union { \
|
|
char dummy[0] __attribute__((deprecated, \
|
|
CPU_ALL_GP(_GP_ENTRY, unused), \
|
|
deprecated)); \
|
|
})
|
|
|
|
/*
|
|
* PORT style (linear pin space)
|
|
*/
|
|
|
|
#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
|
|
|
|
#define PORT_10(pn, fn, pfx, sfx) \
|
|
PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
|
|
PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
|
|
PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
|
|
PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
|
|
PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
|
|
|
|
#define PORT_90(pn, fn, pfx, sfx) \
|
|
PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
|
|
PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
|
|
PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
|
|
PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
|
|
PORT_10(pn+90, fn, pfx##9, sfx)
|
|
|
|
/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
|
|
#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
|
|
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
|
|
|
|
/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
|
|
#define PINMUX_GPIO(_pin) \
|
|
[GPIO_##_pin] = { \
|
|
.pin = (u16)-1, \
|
|
.name = __stringify(GPIO_##_pin), \
|
|
.enum_id = _pin##_DATA, \
|
|
}
|
|
|
|
/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
|
|
#define SH_PFC_PIN_CFG(_pin, cfgs) \
|
|
{ \
|
|
.pin = _pin, \
|
|
.name = __stringify(PORT##_pin), \
|
|
.enum_id = PORT##_pin##_DATA, \
|
|
.configs = cfgs, \
|
|
}
|
|
|
|
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
|
|
* PORT_name_OUT, PORT_name_IN marks
|
|
*/
|
|
#define _PORT_DATA(pn, pfx, sfx) \
|
|
PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
|
|
PORT##pfx##_OUT, PORT##pfx##_IN)
|
|
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
|
|
|
|
/*
|
|
* PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
|
|
*
|
|
* The largest PORT pin index is obtained by taking the size of a union,
|
|
* containing one array per PORT pin, sized by the corresponding pin index.
|
|
* As the fields in the CPU_ALL_PORT() macro definition are separated by
|
|
* commas, while the members of a union must be terminated by semicolons, the
|
|
* commas are absorbed by wrapping them inside dummy attributes.
|
|
*/
|
|
#define _PORT_ENTRY(pn, pfx, sfx) \
|
|
deprecated)); char pfx[pn] __attribute__((deprecated
|
|
#define PORT_ASSIGN_LAST() \
|
|
PORT_LAST = sizeof(union { \
|
|
char dummy[0] __attribute__((deprecated, \
|
|
CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
|
|
deprecated)); \
|
|
})
|
|
|
|
/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
|
|
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
|
|
[gpio - (base)] = { \
|
|
.name = __stringify(gpio), \
|
|
.enum_id = data_or_mark, \
|
|
}
|
|
#define GPIO_FN(str) \
|
|
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
|
|
|
|
/*
|
|
* Pins not associated with a GPIO port
|
|
*/
|
|
|
|
#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
|
|
#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
|
|
|
|
/* NOGP_ALL - Expand to a list of PIN_id */
|
|
#define _NOGP_ALL(pin, name, cfg) PIN_##pin
|
|
#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
|
|
|
|
/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
|
|
#define _NOGP_PINMUX(_pin, _name, cfg) \
|
|
{ \
|
|
.pin = PIN_##_pin, \
|
|
.name = "PIN_" _name, \
|
|
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
|
|
}
|
|
#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
|
|
|
|
/*
|
|
* PORTnCR helper macro for SH-Mobile/R-Mobile
|
|
*/
|
|
#define PORTCR(nr, reg) \
|
|
{ \
|
|
PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
|
|
GROUP(2, 2, 1, 3), \
|
|
GROUP( \
|
|
/* PULMD[1:0], handled by .set_bias() */ \
|
|
0, 0, 0, 0, \
|
|
/* IE and OE */ \
|
|
0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
|
|
/* SEC, not supported */ \
|
|
0, 0, \
|
|
/* PTMD[2:0] */ \
|
|
PORT##nr##_FN0, PORT##nr##_FN1, \
|
|
PORT##nr##_FN2, PORT##nr##_FN3, \
|
|
PORT##nr##_FN4, PORT##nr##_FN5, \
|
|
PORT##nr##_FN6, PORT##nr##_FN7 \
|
|
)) \
|
|
}
|
|
|
|
/*
|
|
* GPIO number helper macro for R-Car
|
|
*/
|
|
#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
|
|
|
|
/*
|
|
* Bias helpers
|
|
*/
|
|
unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
|
|
void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
|
unsigned int bias);
|
|
|
|
unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
|
|
void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
|
unsigned int bias);
|
|
|
|
#endif /* __SH_PFC_H */
|