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991f1372d0
Add separate schema for QDU1000 and QRU1000 interconnect devices to document the different NoCs on these platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221216230914.21771-2-quic_molvera@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H
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#define MASTER_QUP_CORE_0 0
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#define MASTER_QUP_CORE_1 1
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#define SLAVE_QUP_CORE_0 2
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#define SLAVE_QUP_CORE_1 3
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#define MASTER_SYS_TCU 0
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#define MASTER_APPSS_PROC 1
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#define MASTER_GEMNOC_ECPRI_DMA 2
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#define MASTER_FEC_2_GEMNOC 3
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#define MASTER_ANOC_PCIE_GEM_NOC 4
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#define MASTER_SNOC_GC_MEM_NOC 5
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#define MASTER_SNOC_SF_MEM_NOC 6
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#define MASTER_MSS_PROC 7
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#define SLAVE_GEM_NOC_CNOC 8
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#define SLAVE_LLCC 9
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#define SLAVE_GEMNOC_MODEM_CNOC 10
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#define SLAVE_MEM_NOC_PCIE_SNOC 11
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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#define MASTER_GIC_AHB 0
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#define MASTER_QDSS_BAM 1
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#define MASTER_QPIC 2
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#define MASTER_QSPI_0 3
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#define MASTER_QUP_0 4
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#define MASTER_QUP_1 5
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#define MASTER_SNOC_CFG 6
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#define MASTER_ANOC_SNOC 7
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#define MASTER_ANOC_GSI 8
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#define MASTER_GEM_NOC_CNOC 9
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#define MASTER_GEMNOC_MODEM_CNOC 10
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#define MASTER_GEM_NOC_PCIE_SNOC 11
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#define MASTER_CRYPTO 12
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#define MASTER_ECPRI_GSI 13
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#define MASTER_PIMEM 14
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#define MASTER_SNOC_ECPRI_DMA 15
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#define MASTER_GIC 16
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#define MASTER_PCIE 17
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#define MASTER_QDSS_ETR 18
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#define MASTER_QDSS_ETR_1 19
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#define MASTER_SDCC_1 20
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#define MASTER_USB3 21
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#define SLAVE_AHB2PHY_SOUTH 22
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#define SLAVE_AHB2PHY_NORTH 23
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#define SLAVE_AHB2PHY_EAST 24
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#define SLAVE_AOSS 25
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#define SLAVE_CLK_CTL 26
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#define SLAVE_RBCPR_CX_CFG 27
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#define SLAVE_RBCPR_MX_CFG 28
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#define SLAVE_CRYPTO_0_CFG 29
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#define SLAVE_ECPRI_CFG 30
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#define SLAVE_IMEM_CFG 31
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#define SLAVE_IPC_ROUTER_CFG 32
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#define SLAVE_CNOC_MSS 33
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#define SLAVE_PCIE_CFG 34
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#define SLAVE_PDM 35
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#define SLAVE_PIMEM_CFG 36
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#define SLAVE_PRNG 37
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#define SLAVE_QDSS_CFG 38
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#define SLAVE_QPIC 40
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#define SLAVE_QSPI_0 41
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#define SLAVE_QUP_0 42
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#define SLAVE_QUP_1 43
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#define SLAVE_SDCC_2 44
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#define SLAVE_SMBUS_CFG 45
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#define SLAVE_SNOC_CFG 46
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#define SLAVE_TCSR 47
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#define SLAVE_TLMM 48
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#define SLAVE_TME_CFG 49
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#define SLAVE_TSC_CFG 50
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#define SLAVE_USB3_0 51
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#define SLAVE_VSENSE_CTRL_CFG 52
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#define SLAVE_A1NOC_SNOC 53
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#define SLAVE_ANOC_SNOC_GSI 54
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#define SLAVE_DDRSS_CFG 55
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#define SLAVE_ECPRI_GEMNOC 56
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#define SLAVE_SNOC_GEM_NOC_GC 57
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#define SLAVE_SNOC_GEM_NOC_SF 58
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#define SLAVE_MODEM_OFFLINE 59
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#define SLAVE_ANOC_PCIE_GEM_NOC 60
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#define SLAVE_IMEM 61
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#define SLAVE_PIMEM 62
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#define SLAVE_SERVICE_SNOC 63
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#define SLAVE_ETHERNET_SS 64
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#define SLAVE_PCIE_0 65
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#define SLAVE_QDSS_STM 66
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#define SLAVE_TCU 67
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#endif
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