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2f00f7715e
Added documentation for SPDIF IP DT bindings. Signed-off-by: Maruthi Srinivas Bayyavarapu <maruthi.srinivas.bayyavarapu@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
29 lines
915 B
Plaintext
29 lines
915 B
Plaintext
Device-Tree bindings for Xilinx SPDIF IP
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The IP supports playback and capture of SPDIF audio
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Required properties:
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- compatible: "xlnx,spdif-2.0"
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- clock-names: List of input clocks.
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Required elements: "s_axi_aclk", "aud_clk_i"
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- clocks: Input clock specifier. Refer to common clock bindings.
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- reg: Base address and address length of the IP core instance.
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- interrupts-parent: Phandle for interrupt controller.
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- interrupts: List of Interrupt numbers.
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- xlnx,spdif-mode: 0 :- receiver mode
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1 :- transmitter mode
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- xlnx,aud_clk_i: input audio clock value.
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Example:
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spdif_0: spdif@80010000 {
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clock-names = "aud_clk_i", "s_axi_aclk";
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clocks = <&misc_clk_0>, <&clk 71>;
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compatible = "xlnx,spdif-2.0";
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interrupt-names = "spdif_interrupt";
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interrupt-parent = <&gic>;
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interrupts = <0 91 4>;
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reg = <0x0 0x80010000 0x0 0x10000>;
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xlnx,spdif-mode = <1>;
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xlnx,aud_clk_i = <49152913>;
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};
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