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Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231108104343.24192-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
118 lines
3.0 KiB
YAML
118 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/samsung,exynos5433-lpass.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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properties:
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compatible:
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const: samsung,exynos5433-lpass
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'#address-cells':
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const: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: sfr0_ctrl
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power-domains:
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maxItems: 1
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ranges: true
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reg:
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minItems: 2
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maxItems: 2
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'#size-cells':
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const: 1
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patternProperties:
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"^dma-controller@[0-9a-f]+$":
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$ref: /schemas/dma/arm,pl330.yaml
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"^i2s@[0-9a-f]+$":
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$ref: /schemas/sound/samsung-i2s.yaml
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"^serial@[0-9a-f]+$":
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$ref: /schemas/serial/samsung_uart.yaml
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required:
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- compatible
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- '#address-cells'
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- clocks
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- clock-names
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- ranges
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- reg
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- '#size-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5433.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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audio-subsystem@11400000 {
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compatible = "samsung,exynos5433-lpass";
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reg = <0x11400000 0x100>, <0x11500000 0x08>;
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clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
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clock-names = "sfr0_ctrl";
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power-domains = <&pd_aud>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-controller@11420000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x11420000 0x1000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_aud CLK_ACLK_DMAC>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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dma-channels = <8>;
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dma-requests = <32>;
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power-domains = <&pd_aud>;
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};
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i2s@11440000 {
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compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";
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reg = <0x11440000 0x100>;
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dmas = <&adma 0>, <&adma 2>;
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dma-names = "tx", "rx";
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
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<&cmu_aud CLK_SCLK_AUD_I2S>,
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<&cmu_aud CLK_SCLK_I2S_BCLK>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
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#clock-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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power-domains = <&pd_aud>;
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#sound-dai-cells = <1>;
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};
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serial@11460000 {
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compatible = "samsung,exynos5433-uart";
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reg = <0x11460000 0x100>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
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<&cmu_aud CLK_SCLK_AUD_UART>;
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clock-names = "uart", "clk_uart_baud0";
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pinctrl-names = "default";
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pinctrl-0 = <&uart_aud_bus>;
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power-domains = <&pd_aud>;
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};
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};
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