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34059c2570
Handle caching CR3 (from VMX's VMCS) into struct kvm_vcpu via the common
cache_reg() callback and drop the dedicated decache_cr3(). The name
decache_cr3() is somewhat confusing as the caching behavior of CR3
follows that of GPRs, RFLAGS and PDPTRs, (handled via cache_reg()), and
has nothing in common with the caching behavior of CR0/CR4 (whose
decache_cr{0,4}_guest_bits() likely provided the 'decache' verbiage).
This would effectivel adds a BUG() if KVM attempts to cache CR3 on SVM.
Change it to a WARN_ON_ONCE() -- if the cache never requires filling,
the value is already in the right place -- and opportunistically add one
in VMX to provide an equivalent check.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
181 lines
4.7 KiB
C
181 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ASM_KVM_CACHE_REGS_H
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#define ASM_KVM_CACHE_REGS_H
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#include <linux/kvm_host.h>
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#define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS
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#define KVM_POSSIBLE_CR4_GUEST_BITS \
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(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
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| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_PGE)
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#define BUILD_KVM_GPR_ACCESSORS(lname, uname) \
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static __always_inline unsigned long kvm_##lname##_read(struct kvm_vcpu *vcpu)\
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{ \
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return vcpu->arch.regs[VCPU_REGS_##uname]; \
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} \
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static __always_inline void kvm_##lname##_write(struct kvm_vcpu *vcpu, \
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unsigned long val) \
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{ \
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vcpu->arch.regs[VCPU_REGS_##uname] = val; \
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}
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BUILD_KVM_GPR_ACCESSORS(rax, RAX)
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BUILD_KVM_GPR_ACCESSORS(rbx, RBX)
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BUILD_KVM_GPR_ACCESSORS(rcx, RCX)
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BUILD_KVM_GPR_ACCESSORS(rdx, RDX)
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BUILD_KVM_GPR_ACCESSORS(rbp, RBP)
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BUILD_KVM_GPR_ACCESSORS(rsi, RSI)
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BUILD_KVM_GPR_ACCESSORS(rdi, RDI)
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#ifdef CONFIG_X86_64
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BUILD_KVM_GPR_ACCESSORS(r8, R8)
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BUILD_KVM_GPR_ACCESSORS(r9, R9)
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BUILD_KVM_GPR_ACCESSORS(r10, R10)
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BUILD_KVM_GPR_ACCESSORS(r11, R11)
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BUILD_KVM_GPR_ACCESSORS(r12, R12)
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BUILD_KVM_GPR_ACCESSORS(r13, R13)
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BUILD_KVM_GPR_ACCESSORS(r14, R14)
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BUILD_KVM_GPR_ACCESSORS(r15, R15)
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#endif
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static inline bool kvm_register_is_available(struct kvm_vcpu *vcpu,
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enum kvm_reg reg)
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{
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return test_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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}
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static inline bool kvm_register_is_dirty(struct kvm_vcpu *vcpu,
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enum kvm_reg reg)
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{
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return test_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty);
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}
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static inline void kvm_register_mark_available(struct kvm_vcpu *vcpu,
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enum kvm_reg reg)
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{
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__set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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}
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static inline void kvm_register_mark_dirty(struct kvm_vcpu *vcpu,
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enum kvm_reg reg)
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{
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__set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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__set_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty);
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}
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static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
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{
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if (WARN_ON_ONCE((unsigned int)reg >= NR_VCPU_REGS))
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return 0;
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if (!kvm_register_is_available(vcpu, reg))
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kvm_x86_ops->cache_reg(vcpu, reg);
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return vcpu->arch.regs[reg];
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}
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static inline void kvm_register_write(struct kvm_vcpu *vcpu, int reg,
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unsigned long val)
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{
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if (WARN_ON_ONCE((unsigned int)reg >= NR_VCPU_REGS))
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return;
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vcpu->arch.regs[reg] = val;
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kvm_register_mark_dirty(vcpu, reg);
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}
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static inline unsigned long kvm_rip_read(struct kvm_vcpu *vcpu)
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{
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return kvm_register_read(vcpu, VCPU_REGS_RIP);
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}
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static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val)
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{
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kvm_register_write(vcpu, VCPU_REGS_RIP, val);
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}
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static inline unsigned long kvm_rsp_read(struct kvm_vcpu *vcpu)
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{
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return kvm_register_read(vcpu, VCPU_REGS_RSP);
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}
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static inline void kvm_rsp_write(struct kvm_vcpu *vcpu, unsigned long val)
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{
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kvm_register_write(vcpu, VCPU_REGS_RSP, val);
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}
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static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index)
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{
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might_sleep(); /* on svm */
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if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
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kvm_x86_ops->cache_reg(vcpu, VCPU_EXREG_PDPTR);
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return vcpu->arch.walk_mmu->pdptrs[index];
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}
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static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS;
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if (tmask & vcpu->arch.cr0_guest_owned_bits)
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kvm_x86_ops->decache_cr0_guest_bits(vcpu);
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return vcpu->arch.cr0 & mask;
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}
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static inline ulong kvm_read_cr0(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, ~0UL);
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}
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static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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ulong tmask = mask & KVM_POSSIBLE_CR4_GUEST_BITS;
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if (tmask & vcpu->arch.cr4_guest_owned_bits)
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kvm_x86_ops->decache_cr4_guest_bits(vcpu);
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return vcpu->arch.cr4 & mask;
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}
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static inline ulong kvm_read_cr3(struct kvm_vcpu *vcpu)
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{
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if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
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kvm_x86_ops->cache_reg(vcpu, VCPU_EXREG_CR3);
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return vcpu->arch.cr3;
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}
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static inline ulong kvm_read_cr4(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, ~0UL);
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}
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static inline u64 kvm_read_edx_eax(struct kvm_vcpu *vcpu)
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{
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return (kvm_rax_read(vcpu) & -1u)
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| ((u64)(kvm_rdx_read(vcpu) & -1u) << 32);
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}
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static inline void enter_guest_mode(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hflags |= HF_GUEST_MASK;
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}
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static inline void leave_guest_mode(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hflags &= ~HF_GUEST_MASK;
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if (vcpu->arch.load_eoi_exitmap_pending) {
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vcpu->arch.load_eoi_exitmap_pending = false;
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kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
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}
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}
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static inline bool is_guest_mode(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hflags & HF_GUEST_MASK;
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}
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static inline bool is_smm(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hflags & HF_SMM_MASK;
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}
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#endif
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