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f10ee3dcc9
The switch to the user space page tables in the low level ASM code sets
unconditionally bit 12 and bit 11 of CR3. Bit 12 is switching the base
address of the page directory to the user part, bit 11 is switching the
PCID to the PCID associated with the user page tables.
This fails on a machine which lacks PCID support because bit 11 is set in
CR3. Bit 11 is reserved when PCID is inactive.
While the Intel SDM claims that the reserved bits are ignored when PCID is
disabled, the AMD APM states that they should be cleared.
This went unnoticed as the AMD APM was not checked when the code was
developed and reviewed and test systems with Intel CPUs never failed to
boot. The report is against a Centos 6 host where the guest fails to boot,
so it's not yet clear whether this is a virt issue or can happen on real
hardware too, but thats irrelevant as the AMD APM clearly ask for clearing
the reserved bits.
Make sure that on non PCID machines bit 11 is not set by the page table
switching code.
Andy suggested to rename the related bits and masks so they are clearly
describing what they should be used for, which is done as well for clarity.
That split could have been done with alternatives but the macro hell is
horrible and ugly. This can be done on top if someone cares to remove the
extra orq. For now it's a straight forward fix.
Fixes: 6fd166aae7 ("x86/mm: Use/Fix PCID to optimize user/kernel switches")
Reported-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: stable <stable@vger.kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Willy Tarreau <w@1wt.eu>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801140009150.2371@nanos
352 lines
9.4 KiB
C
352 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/jump_label.h>
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#include <asm/unwind_hints.h>
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#include <asm/cpufeatures.h>
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#include <asm/page_types.h>
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#include <asm/percpu.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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/*
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x86 function call convention, 64-bit:
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-------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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---------------------------------------------------------------------------
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rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
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( rsp is obviously invariant across normal function calls. (gcc can 'merge'
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functions when it sees tail-call optimization possibilities) rflags is
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clobbered. Leftover arguments are passed over the stack frame.)
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[*] In the frame-pointers case rbp is fixed to the stack frame.
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[**] for struct return values wider than 64 bits the return convention is a
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bit more complex: up to 128 bits width we return small structures
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straight in rax, rdx. For structures larger than that (3 words or
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larger) the caller puts a pointer to an on-stack return struct
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[allocated in the caller's stack frame] into the first argument - i.e.
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into rdi. All other arguments shift up by one in this case.
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Fortunately this case is rare in the kernel.
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For 32-bit we have the following conventions - kernel is built with
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-mregparm=3 and -freg-struct-return:
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x86 function calling convention, 32-bit:
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----------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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-------------------------------------------------------------------------
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eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
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( here too esp is obviously invariant across normal function calls. eflags
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is clobbered. Leftover arguments are passed over the stack frame. )
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[*] In the frame-pointers case ebp is fixed to the stack frame.
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[**] We build with -freg-struct-return, which on 32-bit means similar
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semantics as on 64-bit: edx can be used for a second return value
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(i.e. covering integer and structure sizes up to 64 bits) - after that
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it gets more complex and more expensive: 3-word or larger struct returns
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get done in the caller's frame and the pointer to the return struct goes
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into regparm0, i.e. eax - the other arguments shift up and the
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function's register parameters degenerate to regparm=2 in essence.
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*/
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#ifdef CONFIG_X86_64
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/*
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* 64-bit system call stack frame layout defines and helpers,
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* for assembly code:
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*/
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/* The layout forms the "struct pt_regs" on the stack: */
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/*
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* C ABI says these regs are callee-preserved. They aren't saved on kernel entry
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* unless syscall needs a complete, fully filled "struct pt_regs".
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*/
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#define R15 0*8
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#define R14 1*8
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#define R13 2*8
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#define R12 3*8
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#define RBP 4*8
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#define RBX 5*8
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/* These regs are callee-clobbered. Always saved on kernel entry. */
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#define R11 6*8
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#define R10 7*8
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#define R9 8*8
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#define R8 9*8
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#define RAX 10*8
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#define RCX 11*8
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#define RDX 12*8
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#define RSI 13*8
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#define RDI 14*8
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/*
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* On syscall entry, this is syscall#. On CPU exception, this is error code.
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* On hw interrupt, it's IRQ number:
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*/
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#define ORIG_RAX 15*8
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/* Return frame for iretq */
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#define RIP 16*8
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#define CS 17*8
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#define EFLAGS 18*8
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#define RSP 19*8
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#define SS 20*8
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#define SIZEOF_PTREGS 21*8
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.macro ALLOC_PT_GPREGS_ON_STACK
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addq $-(15*8), %rsp
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.endm
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.macro SAVE_C_REGS_HELPER offset=0 rax=1 rcx=1 r8910=1 r11=1
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.if \r11
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movq %r11, 6*8+\offset(%rsp)
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.endif
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.if \r8910
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movq %r10, 7*8+\offset(%rsp)
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movq %r9, 8*8+\offset(%rsp)
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movq %r8, 9*8+\offset(%rsp)
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.endif
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.if \rax
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movq %rax, 10*8+\offset(%rsp)
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.endif
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.if \rcx
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movq %rcx, 11*8+\offset(%rsp)
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.endif
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movq %rdx, 12*8+\offset(%rsp)
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movq %rsi, 13*8+\offset(%rsp)
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movq %rdi, 14*8+\offset(%rsp)
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UNWIND_HINT_REGS offset=\offset extra=0
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.endm
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.macro SAVE_C_REGS offset=0
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SAVE_C_REGS_HELPER \offset, 1, 1, 1, 1
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.endm
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.macro SAVE_C_REGS_EXCEPT_RAX_RCX offset=0
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SAVE_C_REGS_HELPER \offset, 0, 0, 1, 1
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.endm
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.macro SAVE_C_REGS_EXCEPT_R891011
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SAVE_C_REGS_HELPER 0, 1, 1, 0, 0
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.endm
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.macro SAVE_C_REGS_EXCEPT_RCX_R891011
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SAVE_C_REGS_HELPER 0, 1, 0, 0, 0
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.endm
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.macro SAVE_C_REGS_EXCEPT_RAX_RCX_R11
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SAVE_C_REGS_HELPER 0, 0, 0, 1, 0
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.endm
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.macro SAVE_EXTRA_REGS offset=0
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movq %r15, 0*8+\offset(%rsp)
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movq %r14, 1*8+\offset(%rsp)
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movq %r13, 2*8+\offset(%rsp)
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movq %r12, 3*8+\offset(%rsp)
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movq %rbp, 4*8+\offset(%rsp)
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movq %rbx, 5*8+\offset(%rsp)
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UNWIND_HINT_REGS offset=\offset
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.endm
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.macro POP_EXTRA_REGS
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popq %r15
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popq %r14
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popq %r13
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popq %r12
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popq %rbp
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popq %rbx
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.endm
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.macro POP_C_REGS
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popq %r11
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popq %r10
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popq %r9
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popq %r8
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popq %rax
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popq %rcx
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popq %rdx
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popq %rsi
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popq %rdi
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.endm
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.macro icebp
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.byte 0xf1
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.endm
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/*
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* This is a sneaky trick to help the unwinder find pt_regs on the stack. The
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* frame pointer is replaced with an encoded pointer to pt_regs. The encoding
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* is just setting the LSB, which makes it an invalid stack address and is also
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* a signal to the unwinder that it's a pt_regs pointer in disguise.
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*
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* NOTE: This macro must be used *after* SAVE_EXTRA_REGS because it corrupts
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* the original rbp.
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*/
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.macro ENCODE_FRAME_POINTER ptregs_offset=0
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#ifdef CONFIG_FRAME_POINTER
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.if \ptregs_offset
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leaq \ptregs_offset(%rsp), %rbp
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.else
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mov %rsp, %rbp
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.endif
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orq $0x1, %rbp
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#endif
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.endm
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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/*
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* PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
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* halves:
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*/
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#define PTI_USER_PGTABLE_BIT PAGE_SHIFT
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#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
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#define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
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#define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
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#define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
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.macro SET_NOFLUSH_BIT reg:req
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bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
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.endm
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.macro ADJUST_KERNEL_CR3 reg:req
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ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
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/* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
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andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
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.endm
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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mov %cr3, \scratch_reg
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ADJUST_KERNEL_CR3 \scratch_reg
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mov \scratch_reg, %cr3
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.Lend_\@:
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.endm
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#define THIS_CPU_user_pcid_flush_mask \
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PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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mov %cr3, \scratch_reg
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* Test if the ASID needs a flush.
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*/
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movq \scratch_reg, \scratch_reg2
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andq $(0x7FF), \scratch_reg /* mask ASID */
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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/* Flush needed, clear the bit */
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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movq \scratch_reg2, \scratch_reg
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jmp .Lwrcr3_pcid_\@
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.Lnoflush_\@:
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movq \scratch_reg2, \scratch_reg
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SET_NOFLUSH_BIT \scratch_reg
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.Lwrcr3_pcid_\@:
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/* Flip the ASID to the user version */
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orq $(PTI_USER_PCID_MASK), \scratch_reg
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.Lwrcr3_\@:
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/* Flip the PGD to the user version */
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orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
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mov \scratch_reg, %cr3
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.Lend_\@:
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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pushq %rax
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SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
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popq %rax
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
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movq %cr3, \scratch_reg
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movq \scratch_reg, \save_reg
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/*
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* Test the user pagetable bit. If set, then the user page tables
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* are active. If clear CR3 already has the kernel page table
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* active.
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*/
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bt $PTI_USER_PGTABLE_BIT, \scratch_reg
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jnc .Ldone_\@
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ADJUST_KERNEL_CR3 \scratch_reg
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movq \scratch_reg, %cr3
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.Ldone_\@:
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.endm
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.macro RESTORE_CR3 scratch_reg:req save_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* KERNEL pages can always resume with NOFLUSH as we do
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* explicit flushes.
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*/
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bt $PTI_USER_PGTABLE_BIT, \save_reg
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jnc .Lnoflush_\@
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/*
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* Check if there's a pending flush for the user ASID we're
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* about to set.
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*/
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movq \save_reg, \scratch_reg
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andq $(0x7FF), \scratch_reg
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jmp .Lwrcr3_\@
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.Lnoflush_\@:
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SET_NOFLUSH_BIT \save_reg
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.Lwrcr3_\@:
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/*
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* The CR3 write could be avoided when not changing its value,
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* but would require a CR3 read *and* a scratch register.
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*/
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movq \save_reg, %cr3
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.Lend_\@:
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.endm
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#else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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.endm
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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.endm
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.macro RESTORE_CR3 scratch_reg:req save_reg:req
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.endm
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#endif
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#endif /* CONFIG_X86_64 */
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/*
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* This does 'call enter_from_user_mode' unless we can avoid it based on
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* kernel config or using the static jump infrastructure.
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*/
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.macro CALL_enter_from_user_mode
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#ifdef CONFIG_CONTEXT_TRACKING
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#ifdef HAVE_JUMP_LABEL
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STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
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#endif
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call enter_from_user_mode
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.Lafter_call_\@:
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#endif
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.endm
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