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a0c9a822bf
Intel spec says that TMR needs to be set/cleared when IRR is set, but kvm also clears it on EOI. I did some tests on a real (AMD based) system, and I see same TMR values both before and after EOI, so I think it's a minor bug in kvm. This patch fixes TMR to be set/cleared on IRR set only as per spec. And now that we don't clear TMR, we can save an atomic read of TMR on EOI that's not propagated to ioapic, by checking whether ioapic needs a specific vector first and calculating the mode afterwards. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
456 lines
11 KiB
C
456 lines
11 KiB
C
/*
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* Copyright (C) 2001 MandrakeSoft S.A.
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*
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* MandrakeSoft S.A.
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* 43, rue d'Aboukir
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* 75002 Paris - France
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* http://www.linux-mandrake.com/
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* http://www.mandrakesoft.com/
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Yunhong Jiang <yunhong.jiang@intel.com>
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* Yaozu (Eddie) Dong <eddie.dong@intel.com>
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* Based on Xen 3.1 code.
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*/
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <linux/smp.h>
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#include <linux/hrtimer.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/current.h>
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#include <trace/events/kvm.h>
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#include "ioapic.h"
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#include "lapic.h"
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#include "irq.h"
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#if 0
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#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
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#else
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#define ioapic_debug(fmt, arg...)
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#endif
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static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
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static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
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unsigned long addr,
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unsigned long length)
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{
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unsigned long result = 0;
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
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| (IOAPIC_VERSION_ID & 0xff));
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break;
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case IOAPIC_REG_APIC_ID:
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case IOAPIC_REG_ARB_ID:
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result = ((ioapic->id & 0xf) << 24);
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break;
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default:
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{
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u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
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u64 redir_content;
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ASSERT(redir_index < IOAPIC_NUM_PINS);
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redir_content = ioapic->redirtbl[redir_index].bits;
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result = (ioapic->ioregsel & 0x1) ?
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(redir_content >> 32) & 0xffffffff :
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redir_content & 0xffffffff;
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break;
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}
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}
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return result;
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}
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static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
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{
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union kvm_ioapic_redirect_entry *pent;
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int injected = -1;
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pent = &ioapic->redirtbl[idx];
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if (!pent->fields.mask) {
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injected = ioapic_deliver(ioapic, idx);
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if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
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pent->fields.remote_irr = 1;
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}
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return injected;
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}
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static void update_handled_vectors(struct kvm_ioapic *ioapic)
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{
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DECLARE_BITMAP(handled_vectors, 256);
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int i;
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memset(handled_vectors, 0, sizeof(handled_vectors));
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for (i = 0; i < IOAPIC_NUM_PINS; ++i)
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__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
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memcpy(ioapic->handled_vectors, handled_vectors,
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sizeof(handled_vectors));
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smp_wmb();
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}
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static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
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{
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unsigned index;
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bool mask_before, mask_after;
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union kvm_ioapic_redirect_entry *e;
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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/* Writes are ignored. */
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break;
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case IOAPIC_REG_APIC_ID:
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ioapic->id = (val >> 24) & 0xf;
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break;
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case IOAPIC_REG_ARB_ID:
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break;
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default:
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index = (ioapic->ioregsel - 0x10) >> 1;
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ioapic_debug("change redir index %x val %x\n", index, val);
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if (index >= IOAPIC_NUM_PINS)
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return;
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e = &ioapic->redirtbl[index];
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mask_before = e->fields.mask;
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if (ioapic->ioregsel & 1) {
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e->bits &= 0xffffffff;
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e->bits |= (u64) val << 32;
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} else {
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e->bits &= ~0xffffffffULL;
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e->bits |= (u32) val;
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e->fields.remote_irr = 0;
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}
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update_handled_vectors(ioapic);
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mask_after = e->fields.mask;
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if (mask_before != mask_after)
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kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
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if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
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&& ioapic->irr & (1 << index))
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ioapic_service(ioapic, index);
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break;
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}
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}
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static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
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{
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union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
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struct kvm_lapic_irq irqe;
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ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
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"vector=%x trig_mode=%x\n",
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entry->fields.dest_id, entry->fields.dest_mode,
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entry->fields.delivery_mode, entry->fields.vector,
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entry->fields.trig_mode);
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irqe.dest_id = entry->fields.dest_id;
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irqe.vector = entry->fields.vector;
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irqe.dest_mode = entry->fields.dest_mode;
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irqe.trig_mode = entry->fields.trig_mode;
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irqe.delivery_mode = entry->fields.delivery_mode << 8;
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irqe.level = 1;
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irqe.shorthand = 0;
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#ifdef CONFIG_X86
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/* Always delivery PIT interrupt to vcpu 0 */
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if (irq == 0) {
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irqe.dest_mode = 0; /* Physical mode. */
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/* need to read apic_id from apic regiest since
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* it can be rewritten */
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irqe.dest_id = ioapic->kvm->bsp_vcpu_id;
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}
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#endif
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return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
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}
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
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{
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u32 old_irr;
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u32 mask = 1 << irq;
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union kvm_ioapic_redirect_entry entry;
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int ret = 1;
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spin_lock(&ioapic->lock);
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old_irr = ioapic->irr;
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if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
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entry = ioapic->redirtbl[irq];
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level ^= entry.fields.polarity;
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if (!level)
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ioapic->irr &= ~mask;
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else {
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int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
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ioapic->irr |= mask;
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if ((edge && old_irr != ioapic->irr) ||
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(!edge && !entry.fields.remote_irr))
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ret = ioapic_service(ioapic, irq);
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else
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ret = 0; /* report coalesced interrupt */
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}
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trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
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}
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spin_unlock(&ioapic->lock);
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return ret;
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}
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static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
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int trigger_mode)
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{
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int i;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
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if (ent->fields.vector != vector)
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continue;
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/*
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* We are dropping lock while calling ack notifiers because ack
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* notifier callbacks for assigned devices call into IOAPIC
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* recursively. Since remote_irr is cleared only after call
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* to notifiers if the same vector will be delivered while lock
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* is dropped it will be put into irr and will be delivered
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* after ack notifier returns.
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*/
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spin_unlock(&ioapic->lock);
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kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
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spin_lock(&ioapic->lock);
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if (trigger_mode != IOAPIC_LEVEL_TRIG)
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continue;
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ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
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ent->fields.remote_irr = 0;
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if (!ent->fields.mask && (ioapic->irr & (1 << i)))
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ioapic_service(ioapic, i);
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}
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}
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bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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smp_rmb();
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return test_bit(vector, ioapic->handled_vectors);
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}
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void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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spin_lock(&ioapic->lock);
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__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
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spin_unlock(&ioapic->lock);
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}
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static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
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{
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return container_of(dev, struct kvm_ioapic, dev);
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}
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static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
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{
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return ((addr >= ioapic->base_address &&
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(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
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}
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static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
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void *val)
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{
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struct kvm_ioapic *ioapic = to_ioapic(this);
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u32 result;
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if (!ioapic_in_range(ioapic, addr))
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return -EOPNOTSUPP;
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ioapic_debug("addr %lx\n", (unsigned long)addr);
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ASSERT(!(addr & 0xf)); /* check alignment */
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addr &= 0xff;
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spin_lock(&ioapic->lock);
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switch (addr) {
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case IOAPIC_REG_SELECT:
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result = ioapic->ioregsel;
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break;
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case IOAPIC_REG_WINDOW:
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result = ioapic_read_indirect(ioapic, addr, len);
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break;
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default:
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result = 0;
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break;
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}
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spin_unlock(&ioapic->lock);
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switch (len) {
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case 8:
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*(u64 *) val = result;
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break;
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case 1:
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case 2:
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case 4:
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memcpy(val, (char *)&result, len);
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break;
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default:
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printk(KERN_WARNING "ioapic: wrong length %d\n", len);
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}
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return 0;
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}
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static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
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const void *val)
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{
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struct kvm_ioapic *ioapic = to_ioapic(this);
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u32 data;
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if (!ioapic_in_range(ioapic, addr))
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return -EOPNOTSUPP;
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ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
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(void*)addr, len, val);
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ASSERT(!(addr & 0xf)); /* check alignment */
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switch (len) {
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case 8:
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case 4:
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data = *(u32 *) val;
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break;
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case 2:
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data = *(u16 *) val;
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break;
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case 1:
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data = *(u8 *) val;
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break;
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default:
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printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
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return 0;
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}
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addr &= 0xff;
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spin_lock(&ioapic->lock);
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switch (addr) {
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case IOAPIC_REG_SELECT:
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ioapic->ioregsel = data & 0xFF; /* 8-bit register */
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break;
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case IOAPIC_REG_WINDOW:
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ioapic_write_indirect(ioapic, data);
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break;
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#ifdef CONFIG_IA64
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case IOAPIC_REG_EOI:
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__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
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break;
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#endif
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default:
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break;
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}
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spin_unlock(&ioapic->lock);
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return 0;
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}
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void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
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{
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int i;
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for (i = 0; i < IOAPIC_NUM_PINS; i++)
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ioapic->redirtbl[i].fields.mask = 1;
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ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
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ioapic->ioregsel = 0;
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ioapic->irr = 0;
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ioapic->id = 0;
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update_handled_vectors(ioapic);
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}
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static const struct kvm_io_device_ops ioapic_mmio_ops = {
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.read = ioapic_mmio_read,
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.write = ioapic_mmio_write,
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};
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int kvm_ioapic_init(struct kvm *kvm)
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{
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struct kvm_ioapic *ioapic;
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int ret;
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ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
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if (!ioapic)
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return -ENOMEM;
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spin_lock_init(&ioapic->lock);
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kvm->arch.vioapic = ioapic;
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kvm_ioapic_reset(ioapic);
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kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
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ioapic->kvm = kvm;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
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IOAPIC_MEM_LENGTH, &ioapic->dev);
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mutex_unlock(&kvm->slots_lock);
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if (ret < 0) {
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kvm->arch.vioapic = NULL;
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kfree(ioapic);
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}
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return ret;
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}
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void kvm_ioapic_destroy(struct kvm *kvm)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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if (ioapic) {
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kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
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kvm->arch.vioapic = NULL;
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kfree(ioapic);
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}
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}
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int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
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{
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struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
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if (!ioapic)
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return -EINVAL;
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spin_lock(&ioapic->lock);
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memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
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spin_unlock(&ioapic->lock);
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return 0;
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}
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int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
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{
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struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
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if (!ioapic)
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return -EINVAL;
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spin_lock(&ioapic->lock);
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memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
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update_handled_vectors(ioapic);
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spin_unlock(&ioapic->lock);
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return 0;
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}
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