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97991657be
Add sh7372 Core Standby sleep mode support and tie it in with the shared SH-Mobile ARM suspend code. The Core Standby mode is the lightest sh7372-specific sleep mode, cutting power to the ARM core excluding the L2 cache. Any interrupt source can be used for wakeups. The low level portion of this code is based on the TI OMAP sleep code in sleep34xx.S, thanks to them. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
261 lines
6.7 KiB
ArmAsm
261 lines
6.7 KiB
ArmAsm
/*
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* sh7372 lowlevel sleep code for "Core Standby Mode"
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*
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* Copyright (C) 2011 Magnus Damm
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*
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* In "Core Standby Mode" the ARM core is off, but L2 cache is still on
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*
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* Based on mach-omap2/sleep34xx.S
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*
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* (C) Copyright 2007 Texas Instruments
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* (C) Copyright 2004 Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#define SMFRAM 0xe6a70000
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.align
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kernel_flush:
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.word v7_flush_dcache_all
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.align 3
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ENTRY(sh7372_cpu_suspend)
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stmfd sp!, {r0-r12, lr} @ save registers on stack
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ldr r8, =SMFRAM
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mov r4, sp @ Store sp
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mrs r5, spsr @ Store spsr
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mov r6, lr @ Store lr
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stmia r8!, {r4-r6}
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mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
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mrc p15, 0, r5, c2, c0, 0 @ TTBR0
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mrc p15, 0, r6, c2, c0, 1 @ TTBR1
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mrc p15, 0, r7, c2, c0, 2 @ TTBCR
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mrc p15, 0, r5, c10, c2, 0 @ PRRR
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mrc p15, 0, r6, c10, c2, 1 @ NMRR
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stmia r8!,{r4-r6}
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mrc p15, 0, r4, c13, c0, 1 @ Context ID
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mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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mrs r7, cpsr @ Store current cpsr
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c1, c0, 0 @ save control register
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stmia r8!, {r4}
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/*
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* jump out to kernel flush routine
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* - reuse that code is better
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* - it executes in a cached space so is faster than refetch per-block
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* - should be faster and will change with kernel
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* - 'might' have to copy address, load and jump to it
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* Flush all data from the L1 data cache before disabling
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* SCTLR.C bit.
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*/
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ldr r1, kernel_flush
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mov lr, pc
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bx r1
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/*
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* Clear the SCTLR.C bit to prevent further data cache
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* allocation. Clearing SCTLR.C would make all the data accesses
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* strongly ordered and would not hit the cache.
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 2) @ Disable the C bit
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mcr p15, 0, r0, c1, c0, 0
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isb
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/*
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* Invalidate L1 data cache. Even though only invalidate is
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* necessary exported flush API is used here. Doing clean
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* on already clean cache would be almost NOP.
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*/
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ldr r1, kernel_flush
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blx r1
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/*
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* The kernel doesn't interwork: v7_flush_dcache_all in particluar will
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* always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
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* This sequence switches back to ARM. Note that .align may insert a
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* nop: bx pc needs to be word-aligned in order to work.
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*/
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THUMB( .thumb )
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THUMB( .align )
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THUMB( bx pc )
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THUMB( nop )
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.arm
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/* Data memory barrier and Data sync barrier */
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dsb
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dmb
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/*
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* ===================================
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* == WFI instruction => Enter idle ==
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* ===================================
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*/
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wfi @ wait for interrupt
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/*
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* ===================================
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* == Resume path for non-OFF modes ==
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* ===================================
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*/
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mrc p15, 0, r0, c1, c0, 0
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tst r0, #(1 << 2) @ Check C bit enabled?
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orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
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mcreq p15, 0, r0, c1, c0, 0
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isb
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/*
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* ===================================
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* == Exit point from non-OFF modes ==
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* ===================================
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*/
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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.pool
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.align 12
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.text
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.global sh7372_cpu_resume
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sh7372_cpu_resume:
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mov r1, #0
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/*
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* Invalidate all instruction caches to PoU
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* and flush branch target cache
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*/
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mcr p15, 0, r1, c7, c5, 0
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ldr r3, =SMFRAM
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ldmia r3!, {r4-r6}
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mov sp, r4 @ Restore sp
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msr spsr_cxsf, r5 @ Restore spsr
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mov lr, r6 @ Restore lr
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ldmia r3!, {r4-r7}
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mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
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mcr p15, 0, r5, c2, c0, 0 @ TTBR0
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mcr p15, 0, r6, c2, c0, 1 @ TTBR1
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mcr p15, 0, r7, c2, c0, 2 @ TTBCR
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ldmia r3!,{r4-r6}
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mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mcr p15, 0, r5, c10, c2, 0 @ PRRR
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mcr p15, 0, r6, c10, c2, 1 @ NMRR
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ldmia r3!,{r4-r7}
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mcr p15, 0, r4, c13, c0, 1 @ Context ID
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mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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msr cpsr, r7 @ store cpsr
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/* Starting to enable MMU here */
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mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
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/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
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and r7, #0x7
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cmp r7, #0x0
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beq usettbr0
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ttbr_error:
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/*
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* More work needs to be done to support N[0:2] value other than 0
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* So looping here so that the error can be detected
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*/
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b ttbr_error
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.align
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cache_pred_disable_mask:
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.word 0xFFFFE7FB
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ttbrbit_mask:
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.word 0xFFFFC000
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table_index_mask:
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.word 0xFFF00000
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table_entry:
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.word 0x00000C02
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usettbr0:
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mrc p15, 0, r2, c2, c0, 0
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ldr r5, ttbrbit_mask
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and r2, r5
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mov r4, pc
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ldr r5, table_index_mask
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and r4, r5 @ r4 = 31 to 20 bits of pc
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/* Extract the value to be written to table entry */
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ldr r6, table_entry
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/* r6 has the value to be written to table entry */
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add r6, r6, r4
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/* Getting the address of table entry to modify */
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lsr r4, #18
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/* r2 has the location which needs to be modified */
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add r2, r4
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ldr r4, [r2]
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str r6, [r2] /* modify the table entry */
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mov r7, r6
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mov r5, r2
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mov r6, r4
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/* r5 = original page table address */
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/* r6 = original page table data */
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
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mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
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mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
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mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
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/*
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* Restore control register. This enables the MMU.
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* The caches and prediction are not enabled here, they
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* will be enabled after restoring the MMU table entry.
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*/
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ldmia r3!, {r4}
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stmia r3!, {r5} /* save original page table address */
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stmia r3!, {r6} /* save original page table data */
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stmia r3!, {r7} /* save modified page table data */
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ldr r2, cache_pred_disable_mask
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and r4, r2
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mcr p15, 0, r4, c1, c0, 0
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dsb
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isb
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ldr r0, =restoremmu_on
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bx r0
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/*
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* ==============================
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* == Exit point from OFF mode ==
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* ==============================
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*/
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restoremmu_on:
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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