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f5e706ad88
With this commit all sparc64 header files are moved to asm-sparc.
The remaining files (71 files) were too different to be trivially
merged so divide them up in a _32.h and a _64.h file which
are both included from the file with no bit size.
The following script were used:
cd include
FILES=`wc -l asm-sparc64/*h | grep -v '^ 1' | cut -b 20-`
for FILE in ${FILES}; do
echo $FILE:
BASE=`echo $FILE | cut -d '.' -f 1`
FN32=${BASE}_32.h
FN64=${BASE}_64.h
GUARD=___ASM_SPARC_`echo $BASE | tr '-' '_' | tr [:lower:] [:upper:]`_H
git mv asm-sparc/$FILE asm-sparc/$FN32
git mv asm-sparc64/$FILE asm-sparc/$FN64
echo git mv done
printf "#ifndef %s\n" $GUARD > asm-sparc/$FILE
printf "#define %s\n" $GUARD >> asm-sparc/$FILE
printf "#if defined(__sparc__) && defined(__arch64__)\n" >> asm-sparc/$FILE
printf "#include <asm-sparc/%s>\n" $FN64 >> asm-sparc/$FILE
printf "#else\n" >> asm-sparc/$FILE
printf "#include <asm-sparc/%s>\n" $FN32 >> asm-sparc/$FILE
printf "#endif\n" >> asm-sparc/$FILE
printf "#endif\n" >> asm-sparc/$FILE
git add asm-sparc/$FILE
echo new file done
printf "#include <asm-sparc/%s>\n" $FILE > asm-sparc64/$FILE
git add asm-sparc64/$FILE
echo sparc64 file done
done
The guard contains three '_' to avoid conflict with existing guards.
In additing the two Kbuild files are emptied to avoid breaking
headers_* targets.
We will reintroduce the exported header files when the necessary
kbuild changes are merged.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
289 lines
12 KiB
C
289 lines
12 KiB
C
/* include/asm-sparc/dma.h
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*
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* Copyright 1995 (C) David S. Miller (davem@davemloft.net)
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*/
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#ifndef _ASM_SPARC_DMA_H
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#define _ASM_SPARC_DMA_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/vac-ops.h> /* for invalidate's, etc. */
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#include <asm/sbus.h>
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#include <asm/delay.h>
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#include <asm/oplib.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <linux/spinlock.h>
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struct page;
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extern spinlock_t dma_spin_lock;
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static inline unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static inline void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* These are irrelevant for Sparc DMA, but we leave it in so that
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* things can compile.
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*/
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#define MAX_DMA_CHANNELS 8
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#define MAX_DMA_ADDRESS (~0UL)
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#define DMA_MODE_READ 1
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#define DMA_MODE_WRITE 2
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/* Useful constants */
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#define SIZE_16MB (16*1024*1024)
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#define SIZE_64K (64*1024)
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/* SBUS DMA controller reg offsets */
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#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
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#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
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#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
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#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
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/* DVMA chip revisions */
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enum dvma_rev {
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dvmarev0,
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dvmaesc1,
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dvmarev1,
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dvmarev2,
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dvmarev3,
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dvmarevplus,
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dvmahme
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};
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#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
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/* Linux DMA information structure, filled during probe. */
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struct sbus_dma {
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struct sbus_dma *next;
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struct sbus_dev *sdev;
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void __iomem *regs;
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/* Status, misc info */
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int node; /* Prom node for this DMA device */
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int running; /* Are we doing DMA now? */
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int allocated; /* Are we "owned" by anyone yet? */
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/* Transfer information. */
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unsigned long addr; /* Start address of current transfer */
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int nbytes; /* Size of current transfer */
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int realbytes; /* For splitting up large transfers, etc. */
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/* DMA revision */
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enum dvma_rev revision;
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};
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extern struct sbus_dma *dma_chain;
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/* Broken hardware... */
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#ifdef CONFIG_SUN4
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/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
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* Or is rev0 present only on sun4 boxes? -jj */
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#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
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#else
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#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
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#endif
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#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
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/* Main routines in dma.c */
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extern void dvma_init(struct sbus_bus *);
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/* Fields in the cond_reg register */
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/* First, the version identification bits */
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#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
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#define DMA_VERS0 0x00000000 /* Sunray DMA version */
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#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
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#define DMA_VERS1 0x80000000 /* DMA rev 1 */
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#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
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#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
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#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
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#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
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#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
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#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
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#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
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#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
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#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
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#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
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#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
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#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
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#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
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#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
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#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
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#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
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#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
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#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
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#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
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#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
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#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
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#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
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#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
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#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
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#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
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#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
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#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
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#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
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#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
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#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
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#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
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#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
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#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
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#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
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#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
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#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
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#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
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#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
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#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
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#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
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#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
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#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
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#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
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#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
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#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
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#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
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/* Values describing the burst-size property from the PROM */
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#define DMA_BURST1 0x01
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#define DMA_BURST2 0x02
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#define DMA_BURST4 0x04
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#define DMA_BURST8 0x08
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#define DMA_BURST16 0x10
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#define DMA_BURST32 0x20
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#define DMA_BURST64 0x40
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#define DMA_BURSTBITS 0x7f
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/* Determine highest possible final transfer address given a base */
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#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
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/* Yes, I hack a lot of elisp in my spare time... */
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#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
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#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
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#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
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#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
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#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
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#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
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#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
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#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
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#define DMA_BEGINDMA_W(regs) \
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((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
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#define DMA_BEGINDMA_R(regs) \
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((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
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/* For certain DMA chips, we need to disable ints upon irq entry
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* and turn them back on when we are done. So in any ESP interrupt
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* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
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* when leaving the handler. You have been warned...
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*/
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#define DMA_IRQ_ENTRY(dma, dregs) do { \
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if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
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} while (0)
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#define DMA_IRQ_EXIT(dma, dregs) do { \
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if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
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} while(0)
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#if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
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/* Pause until counter runs out or BIT isn't set in the DMA condition
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* register.
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*/
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static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
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unsigned long bit)
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{
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int ctr = 50000; /* Let's find some bugs ;) */
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/* Busy wait until the bit is not set any more */
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while((regs->cond_reg&bit) && (ctr>0)) {
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ctr--;
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__delay(5);
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}
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/* Check for bogus outcome. */
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if(!ctr)
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panic("DMA timeout");
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}
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/* Reset the friggin' thing... */
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#define DMA_RESET(dma) do { \
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struct sparc_dma_registers *regs = dma->regs; \
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/* Let the current FIFO drain itself */ \
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sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
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/* Reset the logic */ \
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regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
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__delay(400); /* let the bits set ;) */ \
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regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
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sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
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/* Enable FAST transfers if available */ \
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if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
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dma->running = 0; \
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} while(0)
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#endif
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#define for_each_dvma(dma) \
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for((dma) = dma_chain; (dma); (dma) = (dma)->next)
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extern int get_dma_list(char *);
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extern int request_dma(unsigned int, __const__ char *);
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extern void free_dma(unsigned int);
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/* From PCI */
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#else
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#define isa_dma_bridge_buggy (0)
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#endif
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/* Routines for data transfer buffers. */
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BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
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BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
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#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
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#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
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/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
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BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
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BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
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BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
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BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
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#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
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#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
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#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
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#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
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/*
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* mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
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*
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* The mmu_map_dma_area establishes two mappings in one go.
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* These mappings point to pages normally mapped at 'va' (linear address).
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* First mapping is for CPU visible address at 'a', uncached.
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* This is an alias, but it works because it is an uncached mapping.
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* Second mapping is for device visible address, or "bus" address.
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* The bus address is returned at '*pba'.
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*
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* These functions seem distinct, but are hard to split. On sun4c,
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* at least for now, 'a' is equal to bus address, and retured in *pba.
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* On sun4m, page attributes depend on the CPU type, so we have to
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* know if we are mapping RAM or I/O, so it has to be an additional argument
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* to a separate mapping function for CPU visible mappings.
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*/
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BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
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BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
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BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len)
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#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
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#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
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#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba)
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#endif /* !(_ASM_SPARC_DMA_H) */
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