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8e02c3b782
Currently, only TLB-based ioremap() support writecombine, so add the counterpart for DMW-based ioremap() with help of DMW2. The base address (WRITECOMBINE_BASE) is configured as 0xa000000000000000. DMW3 is unused by kernel now, however firmware may leave garbage in them and interfere kernel's address mapping. So clear it as necessary. BTW, centralize the DMW configuration to macro SETUP_DMWINS. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
136 lines
2.9 KiB
C
136 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1996, 99 Ralf Baechle
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* Copyright (C) 2000, 2002 Maciej W. Rozycki
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* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
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*/
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#ifndef _ASM_ADDRSPACE_H
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#define _ASM_ADDRSPACE_H
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#include <linux/const.h>
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#include <linux/sizes.h>
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#include <asm/loongarch.h>
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/*
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* This gives the physical RAM offset.
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*/
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#ifndef __ASSEMBLY__
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#ifndef PHYS_OFFSET
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#define PHYS_OFFSET _UL(0)
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#endif
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extern unsigned long vm_map_base;
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#endif /* __ASSEMBLY__ */
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#ifndef IO_BASE
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#define IO_BASE CSR_DMW0_BASE
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#endif
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#ifndef CACHE_BASE
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#define CACHE_BASE CSR_DMW1_BASE
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#endif
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#ifndef UNCACHE_BASE
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#define UNCACHE_BASE CSR_DMW0_BASE
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#endif
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#ifndef WRITECOMBINE_BASE
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#define WRITECOMBINE_BASE CSR_DMW2_BASE
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#endif
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#define DMW_PABITS 48
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#define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1)
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/*
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* Memory above this physical address will be considered highmem.
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*/
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#ifndef HIGHMEM_START
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#define HIGHMEM_START (_UL(1) << _UL(DMW_PABITS))
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#endif
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#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
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#define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
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#define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
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/*
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* This handles the memory map.
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*/
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#ifndef PAGE_OFFSET
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#define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
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#endif
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#ifndef FIXADDR_TOP
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#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
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#endif
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#ifdef __ASSEMBLY__
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#define _ATYPE_
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#define _ATYPE32_
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#define _ATYPE64_
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#else
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#define _ATYPE_ __PTRDIFF_TYPE__
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#define _ATYPE32_ int
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#define _ATYPE64_ __s64
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#endif
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#ifdef CONFIG_64BIT
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#define _CONST64_(x) _UL(x)
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#else
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#define _CONST64_(x) _ULL(x)
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#endif
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/*
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* 32/64-bit LoongArch address spaces
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*/
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#ifdef __ASSEMBLY__
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#define _ACAST32_
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#define _ACAST64_
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#else
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#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
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#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
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#endif
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#ifdef CONFIG_32BIT
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#define UVRANGE 0x00000000
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#define KPRANGE0 0x80000000
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#define KPRANGE1 0xa0000000
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#define KVRANGE 0xc0000000
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#else
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#define XUVRANGE _CONST64_(0x0000000000000000)
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#define XSPRANGE _CONST64_(0x4000000000000000)
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#define XKPRANGE _CONST64_(0x8000000000000000)
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#define XKVRANGE _CONST64_(0xc000000000000000)
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#endif
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/*
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* Returns the physical address of a KPRANGEx / XKPRANGE address
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*/
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#define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
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/*
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* On LoongArch, I/O ports mappring is following:
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*
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* | .... |
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* |-----------------------|
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* | pci io ports(16K~32M) |
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* |-----------------------|
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* | isa io ports(0 ~16K) |
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* PCI_IOBASE ->|-----------------------|
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* | .... |
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*/
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#define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
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#define PCI_IOSIZE SZ_32M
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#define ISA_IOSIZE SZ_16K
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#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
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#define PHYS_LINK_KADDR PHYSADDR(VMLINUX_LOAD_ADDRESS)
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#endif /* _ASM_ADDRSPACE_H */
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