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Document power-domains, operating-points-v2 and interconnects to allow making performance state votes for certain clock frequencies of the UART DM controller. The interconnect path to DRAM is needed when UART DM is used together with a DMA engine. Voting for these shared resources is necessary to guarantee performance with power management enabled. Otherwise these resources might run at minimal performance state which is not sufficient for certain UART baud rates. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231128-serial-msm-dvfs-v1-1-4f290d20a4be@kernkonzept.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
126 lines
3.2 KiB
YAML
126 lines
3.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm MSM Serial UARTDM
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description: |
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The MSM serial UARTDM hardware is designed for high-speed use cases where the
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transmit and/or receive channels can be offloaded to a dma-engine. From a
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software perspective it's mostly compatible with the MSM serial UART except
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that it supports reading and writing multiple characters at a time.
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Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
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The alias serialN will result in the UART being assigned port N. If any
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serialN alias exists, then an alias must exist for each enabled UART. The
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serialN aliases should be in a .dts file instead of in a .dtsi file.
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm-uartdm-v1.1
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- qcom,msm-uartdm-v1.2
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- qcom,msm-uartdm-v1.3
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- qcom,msm-uartdm-v1.4
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- const: qcom,msm-uartdm
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: iface
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interconnects:
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maxItems: 1
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interrupts:
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maxItems: 1
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operating-points-v2: true
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power-domains:
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maxItems: 1
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qcom,rx-crci:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Identificator for Client Rate Control Interface to be used with RX DMA
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channel. Required when using DMA for reception with UARTDM v1.3 and
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below.
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qcom,tx-crci:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Identificator for Client Rate Control Interface to be used with TX DMA
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channel. Required when using DMA for transmission with UARTDM v1.3 and
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below.
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reg:
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minItems: 1
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items:
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- description: Main control registers
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- description: An optional second register location shall specify the GSBI control region.
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required:
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- compatible
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- clock-names
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- clocks
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- interrupts
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- reg
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allOf:
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- $ref: /schemas/serial/serial.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: qcom,msm-uartdm-v1.3
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then:
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properties:
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reg:
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minItems: 2
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else:
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properties:
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reg:
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maxItems: 1
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interconnect/qcom,msm8996.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
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clock-names = "core", "iface";
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dmas = <&dma0 0>, <&dma0 1>;
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dma-names = "tx", "rx";
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power-domains = <&rpmpd MSM8996_VDDCX>;
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operating-points-v2 = <&uart_opp_table>;
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interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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};
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