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942e02e150
The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, and implements the not yet frozen ACLINT spec. This spec seems to be abandoned, and will not be frozen in the predictable future. Frozen specs required by the RISC-V maintainers before merging content relating to those extensions, therefore a generic compatible is not appropriate. Instead, add new vendor specific compatible strings to identify mswi of sg2042 clint. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [conor: re-wrote commit message to drop irrelevant sifive,clint discussion] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
44 lines
981 B
YAML
44 lines
981 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
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maintainers:
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- Inochi Amaoto <inochiama@outlook.com>
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properties:
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compatible:
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items:
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- enum:
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- sophgo,sg2042-aclint-mswi
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- const: thead,c900-aclint-mswi
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reg:
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maxItems: 1
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interrupts-extended:
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minItems: 1
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maxItems: 4095
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts-extended
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examples:
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- |
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interrupt-controller@94000000 {
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compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
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interrupts-extended = <&cpu1intc 3>,
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<&cpu2intc 3>,
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<&cpu3intc 3>,
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<&cpu4intc 3>;
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reg = <0x94000000 0x00010000>;
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};
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...
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