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3e9a6321f9
window to remove most of the remaining plat includes to get us closer to ARM common zImage support. To avoid a huge amount of trivial merge conflicts with includes, this branch is based on several small topic branches coordinated with the driver subsystem maintainers. These branches are based on v3.7-rc1 and can also be merged into the related driver subsystem branches as needed: omap-for-v3.8/cleanup-headers-prepare few trivial driver changes omap-for-v3.8/cleanup-headers-dma move of the DMA header omap-for-v3.8/cleanup-headers-gpmc GPMC and MTD changes omap-for-v3.8/cleanup-headers-mmc MMC related changes omap-for-v3.8/cleanup-headers-dss DSS related changes omap-for-v3.8/cleanup-headers-asoc ASoC related changes Note that for the dma-omap.h, it was decided that it should be is completed. For the related discussion, please see: https://patchwork.kernel.org/patch/1519591/# After these patches we still have a few plat headers remaining that will be handled in later pull requests. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQgLn6AAoJEBvUPslcq6VztJIQAMDLmUr4XRa0pV9ASPieMSnP LqXQ8Gpr8JP6I2A7mjj5K/PVvU2PCIgefX5/F7PssWeDzPs1p6T5eQc6/Oo88j+k 6xIaPJtuU6aiMKiH4QJBU9mfFZN4tvKNX8sJZ4YhzAmkKshwSd2XdWQlkSWYV7Ii QFRXOdYdX3dgvt3Pv5LYhFMlRDzXlMtCNkdyO0C5yDc038FvT5kxcgpOJ99ndX1F aSpNPchDwEXP7WZl3O7uZs732hRHQbKraMkzalVJ5mgvLSwF7VsB+BLdjOgRqFfg edpAPt/izpTk7cg7RQiItrW3xz3eSiN/fiAg2wLvxr6ewzB5DguPLa6DNPF+uyup BlpQAvNsICIixfKb/qimQBOkB71TTRxqvBnG0Vt/cExS1dTuWlhyCYzA6dhZtl+w 7ETCo7Mmj+L9T1EfzhMPgjWvMZ4Luli4NHSUYxMl5Cs8nu1y6ytIXxH9e0mnZAbK n4ANoIuFE3ZueXWnHAVCOs0YZj2F1OLB+mFkIFg3OVpB4WCXiOTgJuDNsAAQNS3/ VsYVehNFRB/E/lMWkN293j95LRSwl/sIKbvlpxe7M3XQi4IWh1bDPwcg1YhGPxRV HIuQSSMIIzcsFoDqbQYv9qzpvslfee58fBV0L8BzMyXNd1lYzWJ5Af6A8ddSVVFS Hh+btZObC1zP/2IKbImk =HUTj -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.8/cleanup-headers-signed' into omap-for-v3.8/cleanup-headers-serial-take2 This is the first set of omap cleanup patches for v3.8 merge window to remove most of the remaining plat includes to get us closer to ARM common zImage support. To avoid a huge amount of trivial merge conflicts with includes, this branch is based on several small topic branches coordinated with the driver subsystem maintainers. These branches are based on v3.7-rc1 and can also be merged into the related driver subsystem branches as needed: omap-for-v3.8/cleanup-headers-prepare few trivial driver changes omap-for-v3.8/cleanup-headers-dma move of the DMA header omap-for-v3.8/cleanup-headers-gpmc GPMC and MTD changes omap-for-v3.8/cleanup-headers-mmc MMC related changes omap-for-v3.8/cleanup-headers-dss DSS related changes omap-for-v3.8/cleanup-headers-asoc ASoC related changes Note that for the dma-omap.h, it was decided that it should be is completed. For the related discussion, please see: https://patchwork.kernel.org/patch/1519591/# After these patches we still have a few plat headers remaining that will be handled in later pull requests.
942 lines
22 KiB
C
942 lines
22 KiB
C
/*
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* GPMC support functions
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*
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* Copyright (C) 2005-2006 Nokia Corporation
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*
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* Author: Juha Yrjola
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/ioport.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/mtd-nand-omap2.h>
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#include <asm/mach-types.h>
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#include "soc.h"
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#include "common.h"
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#include "omap_device.h"
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#include "gpmc.h"
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#define DEVICE_NAME "omap-gpmc"
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/* GPMC register offsets */
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#define GPMC_REVISION 0x00
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#define GPMC_SYSCONFIG 0x10
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#define GPMC_SYSSTATUS 0x14
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#define GPMC_IRQSTATUS 0x18
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#define GPMC_IRQENABLE 0x1c
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#define GPMC_TIMEOUT_CONTROL 0x40
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#define GPMC_ERR_ADDRESS 0x44
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#define GPMC_ERR_TYPE 0x48
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#define GPMC_CONFIG 0x50
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#define GPMC_STATUS 0x54
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#define GPMC_PREFETCH_CONFIG1 0x1e0
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#define GPMC_PREFETCH_CONFIG2 0x1e4
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#define GPMC_PREFETCH_CONTROL 0x1ec
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#define GPMC_PREFETCH_STATUS 0x1f0
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#define GPMC_ECC_CONFIG 0x1f4
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#define GPMC_ECC_CONTROL 0x1f8
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#define GPMC_ECC_SIZE_CONFIG 0x1fc
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#define GPMC_ECC1_RESULT 0x200
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#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
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#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
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#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
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#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
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/* GPMC ECC control settings */
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#define GPMC_ECC_CTRL_ECCCLEAR 0x100
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#define GPMC_ECC_CTRL_ECCDISABLE 0x000
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#define GPMC_ECC_CTRL_ECCREG1 0x001
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#define GPMC_ECC_CTRL_ECCREG2 0x002
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#define GPMC_ECC_CTRL_ECCREG3 0x003
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#define GPMC_ECC_CTRL_ECCREG4 0x004
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#define GPMC_ECC_CTRL_ECCREG5 0x005
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#define GPMC_ECC_CTRL_ECCREG6 0x006
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#define GPMC_ECC_CTRL_ECCREG7 0x007
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#define GPMC_ECC_CTRL_ECCREG8 0x008
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#define GPMC_ECC_CTRL_ECCREG9 0x009
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#define GPMC_CS0_OFFSET 0x60
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#define GPMC_CS_SIZE 0x30
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#define GPMC_BCH_SIZE 0x10
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#define GPMC_MEM_START 0x00000000
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#define GPMC_MEM_END 0x3FFFFFFF
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#define BOOT_ROM_SPACE 0x100000 /* 1MB */
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#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
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#define GPMC_SECTION_SHIFT 28 /* 128 MB */
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#define CS_NUM_SHIFT 24
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#define ENABLE_PREFETCH (0x1 << 7)
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#define DMA_MPU_MODE 2
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#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
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#define GPMC_REVISION_MINOR(l) (l & 0xf)
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#define GPMC_HAS_WR_ACCESS 0x1
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#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
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/* XXX: Only NAND irq has been considered,currently these are the only ones used
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*/
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#define GPMC_NR_IRQ 2
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struct gpmc_client_irq {
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unsigned irq;
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u32 bitmask;
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};
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/* Structure to save gpmc cs context */
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struct gpmc_cs_config {
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u32 config1;
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u32 config2;
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u32 config3;
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u32 config4;
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u32 config5;
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u32 config6;
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u32 config7;
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int is_valid;
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};
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/*
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* Structure to save/restore gpmc context
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* to support core off on OMAP3
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*/
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struct omap3_gpmc_regs {
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u32 sysconfig;
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u32 irqenable;
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u32 timeout_ctrl;
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u32 config;
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u32 prefetch_config1;
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u32 prefetch_config2;
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u32 prefetch_control;
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struct gpmc_cs_config cs_context[GPMC_CS_NUM];
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};
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static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
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static struct irq_chip gpmc_irq_chip;
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static unsigned gpmc_irq_start;
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static struct resource gpmc_mem_root;
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static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
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static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
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static struct device *gpmc_dev;
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static int gpmc_irq;
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static resource_size_t phys_base, mem_size;
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static unsigned gpmc_capability;
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static void __iomem *gpmc_base;
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static struct clk *gpmc_l3_clk;
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static irqreturn_t gpmc_handle_irq(int irq, void *dev);
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static void gpmc_write_reg(int idx, u32 val)
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{
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__raw_writel(val, gpmc_base + idx);
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}
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static u32 gpmc_read_reg(int idx)
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{
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return __raw_readl(gpmc_base + idx);
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}
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void gpmc_cs_write_reg(int cs, int idx, u32 val)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
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__raw_writel(val, reg_addr);
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}
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u32 gpmc_cs_read_reg(int cs, int idx)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
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return __raw_readl(reg_addr);
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}
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/* TODO: Add support for gpmc_fck to clock framework and use it */
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unsigned long gpmc_get_fclk_period(void)
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{
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unsigned long rate = clk_get_rate(gpmc_l3_clk);
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if (rate == 0) {
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printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
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return 0;
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}
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rate /= 1000;
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rate = 1000000000 / rate; /* In picoseconds */
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return rate;
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}
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unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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return (time_ns * 1000 + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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return (time_ps + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_ticks_to_ns(unsigned int ticks)
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{
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return ticks * gpmc_get_fclk_period() / 1000;
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}
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unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
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{
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unsigned long ticks = gpmc_ns_to_ticks(time_ns);
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return ticks * gpmc_get_fclk_period() / 1000;
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}
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#ifdef DEBUG
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static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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int time, const char *name)
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#else
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static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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int time)
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#endif
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{
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u32 l;
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int ticks, mask, nr_bits;
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if (time == 0)
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ticks = 0;
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else
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ticks = gpmc_ns_to_ticks(time);
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nr_bits = end_bit - st_bit + 1;
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if (ticks >= 1 << nr_bits) {
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#ifdef DEBUG
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printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
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cs, name, time, ticks, 1 << nr_bits);
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#endif
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return -1;
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}
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mask = (1 << nr_bits) - 1;
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l = gpmc_cs_read_reg(cs, reg);
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#ifdef DEBUG
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printk(KERN_INFO
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"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
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cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
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(l >> st_bit) & mask, time);
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#endif
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l &= ~(mask << st_bit);
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l |= ticks << st_bit;
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gpmc_cs_write_reg(cs, reg, l);
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return 0;
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}
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#ifdef DEBUG
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#define GPMC_SET_ONE(reg, st, end, field) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
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t->field, #field) < 0) \
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return -1
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#else
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#define GPMC_SET_ONE(reg, st, end, field) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
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return -1
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#endif
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int gpmc_calc_divider(unsigned int sync_clk)
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{
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int div;
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u32 l;
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l = sync_clk + (gpmc_get_fclk_period() - 1);
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div = l / gpmc_get_fclk_period();
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if (div > 4)
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return -1;
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if (div <= 0)
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div = 1;
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return div;
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}
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int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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{
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int div;
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u32 l;
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div = gpmc_calc_divider(t->sync_clk);
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if (div < 0)
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return div;
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
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if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
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if (gpmc_capability & GPMC_HAS_WR_ACCESS)
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
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/* caller is expected to have initialized CONFIG1 to cover
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* at least sync vs async
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*/
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
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#ifdef DEBUG
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printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
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cs, (div * gpmc_get_fclk_period()) / 1000, div);
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#endif
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l &= ~0x03;
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l |= (div - 1);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
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}
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return 0;
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}
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static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
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{
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u32 l;
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u32 mask;
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mask = (1 << GPMC_SECTION_SHIFT) - size;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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l &= ~0x3f;
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l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
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l &= ~(0x0f << 8);
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l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
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l |= GPMC_CONFIG7_CSVALID;
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
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}
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static void gpmc_cs_disable_mem(int cs)
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{
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u32 l;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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l &= ~GPMC_CONFIG7_CSVALID;
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
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}
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static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
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{
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u32 l;
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u32 mask;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
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mask = (l >> 8) & 0x0f;
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*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
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}
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static int gpmc_cs_mem_enabled(int cs)
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{
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u32 l;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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return l & GPMC_CONFIG7_CSVALID;
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}
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int gpmc_cs_set_reserved(int cs, int reserved)
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{
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if (cs > GPMC_CS_NUM)
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return -ENODEV;
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gpmc_cs_map &= ~(1 << cs);
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gpmc_cs_map |= (reserved ? 1 : 0) << cs;
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return 0;
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}
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int gpmc_cs_reserved(int cs)
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{
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if (cs > GPMC_CS_NUM)
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return -ENODEV;
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return gpmc_cs_map & (1 << cs);
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}
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static unsigned long gpmc_mem_align(unsigned long size)
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{
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int order;
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size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
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order = GPMC_CHUNK_SHIFT - 1;
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do {
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size >>= 1;
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order++;
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} while (size);
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size = 1 << order;
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return size;
|
|
}
|
|
|
|
static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
|
|
{
|
|
struct resource *res = &gpmc_cs_mem[cs];
|
|
int r;
|
|
|
|
size = gpmc_mem_align(size);
|
|
spin_lock(&gpmc_mem_lock);
|
|
res->start = base;
|
|
res->end = base + size - 1;
|
|
r = request_resource(&gpmc_mem_root, res);
|
|
spin_unlock(&gpmc_mem_lock);
|
|
|
|
return r;
|
|
}
|
|
|
|
static int gpmc_cs_delete_mem(int cs)
|
|
{
|
|
struct resource *res = &gpmc_cs_mem[cs];
|
|
int r;
|
|
|
|
spin_lock(&gpmc_mem_lock);
|
|
r = release_resource(&gpmc_cs_mem[cs]);
|
|
res->start = 0;
|
|
res->end = 0;
|
|
spin_unlock(&gpmc_mem_lock);
|
|
|
|
return r;
|
|
}
|
|
|
|
int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
|
|
{
|
|
struct resource *res = &gpmc_cs_mem[cs];
|
|
int r = -1;
|
|
|
|
if (cs > GPMC_CS_NUM)
|
|
return -ENODEV;
|
|
|
|
size = gpmc_mem_align(size);
|
|
if (size > (1 << GPMC_SECTION_SHIFT))
|
|
return -ENOMEM;
|
|
|
|
spin_lock(&gpmc_mem_lock);
|
|
if (gpmc_cs_reserved(cs)) {
|
|
r = -EBUSY;
|
|
goto out;
|
|
}
|
|
if (gpmc_cs_mem_enabled(cs))
|
|
r = adjust_resource(res, res->start & ~(size - 1), size);
|
|
if (r < 0)
|
|
r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
|
|
size, NULL, NULL);
|
|
if (r < 0)
|
|
goto out;
|
|
|
|
gpmc_cs_enable_mem(cs, res->start, resource_size(res));
|
|
*base = res->start;
|
|
gpmc_cs_set_reserved(cs, 1);
|
|
out:
|
|
spin_unlock(&gpmc_mem_lock);
|
|
return r;
|
|
}
|
|
EXPORT_SYMBOL(gpmc_cs_request);
|
|
|
|
void gpmc_cs_free(int cs)
|
|
{
|
|
spin_lock(&gpmc_mem_lock);
|
|
if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
|
|
printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
|
|
BUG();
|
|
spin_unlock(&gpmc_mem_lock);
|
|
return;
|
|
}
|
|
gpmc_cs_disable_mem(cs);
|
|
release_resource(&gpmc_cs_mem[cs]);
|
|
gpmc_cs_set_reserved(cs, 0);
|
|
spin_unlock(&gpmc_mem_lock);
|
|
}
|
|
EXPORT_SYMBOL(gpmc_cs_free);
|
|
|
|
/**
|
|
* gpmc_cs_configure - write request to configure gpmc
|
|
* @cs: chip select number
|
|
* @cmd: command type
|
|
* @wval: value to write
|
|
* @return status of the operation
|
|
*/
|
|
int gpmc_cs_configure(int cs, int cmd, int wval)
|
|
{
|
|
int err = 0;
|
|
u32 regval = 0;
|
|
|
|
switch (cmd) {
|
|
case GPMC_ENABLE_IRQ:
|
|
gpmc_write_reg(GPMC_IRQENABLE, wval);
|
|
break;
|
|
|
|
case GPMC_SET_IRQ_STATUS:
|
|
gpmc_write_reg(GPMC_IRQSTATUS, wval);
|
|
break;
|
|
|
|
case GPMC_CONFIG_WP:
|
|
regval = gpmc_read_reg(GPMC_CONFIG);
|
|
if (wval)
|
|
regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
|
|
else
|
|
regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
|
|
gpmc_write_reg(GPMC_CONFIG, regval);
|
|
break;
|
|
|
|
case GPMC_CONFIG_RDY_BSY:
|
|
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
|
if (wval)
|
|
regval |= WR_RD_PIN_MONITORING;
|
|
else
|
|
regval &= ~WR_RD_PIN_MONITORING;
|
|
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
|
|
break;
|
|
|
|
case GPMC_CONFIG_DEV_SIZE:
|
|
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
|
|
|
/* clear 2 target bits */
|
|
regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
|
|
|
|
/* set the proper value */
|
|
regval |= GPMC_CONFIG1_DEVICESIZE(wval);
|
|
|
|
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
|
|
break;
|
|
|
|
case GPMC_CONFIG_DEV_TYPE:
|
|
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
|
regval |= GPMC_CONFIG1_DEVICETYPE(wval);
|
|
if (wval == GPMC_DEVICETYPE_NOR)
|
|
regval |= GPMC_CONFIG1_MUXADDDATA;
|
|
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
|
|
err = -EINVAL;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(gpmc_cs_configure);
|
|
|
|
void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
|
|
{
|
|
int i;
|
|
|
|
reg->gpmc_status = gpmc_base + GPMC_STATUS;
|
|
reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
|
|
GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
|
|
reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
|
|
GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
|
|
reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
|
|
GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
|
|
reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
|
|
reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
|
|
reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
|
|
reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
|
|
reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
|
|
reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
|
|
reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
|
|
reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
|
|
|
|
for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
|
|
reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
|
|
GPMC_BCH_SIZE * i;
|
|
reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
|
|
GPMC_BCH_SIZE * i;
|
|
reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
|
|
GPMC_BCH_SIZE * i;
|
|
reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
|
|
GPMC_BCH_SIZE * i;
|
|
}
|
|
}
|
|
|
|
int gpmc_get_client_irq(unsigned irq_config)
|
|
{
|
|
int i;
|
|
|
|
if (hweight32(irq_config) > 1)
|
|
return 0;
|
|
|
|
for (i = 0; i < GPMC_NR_IRQ; i++)
|
|
if (gpmc_client_irq[i].bitmask & irq_config)
|
|
return gpmc_client_irq[i].irq;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gpmc_irq_endis(unsigned irq, bool endis)
|
|
{
|
|
int i;
|
|
u32 regval;
|
|
|
|
for (i = 0; i < GPMC_NR_IRQ; i++)
|
|
if (irq == gpmc_client_irq[i].irq) {
|
|
regval = gpmc_read_reg(GPMC_IRQENABLE);
|
|
if (endis)
|
|
regval |= gpmc_client_irq[i].bitmask;
|
|
else
|
|
regval &= ~gpmc_client_irq[i].bitmask;
|
|
gpmc_write_reg(GPMC_IRQENABLE, regval);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gpmc_irq_disable(struct irq_data *p)
|
|
{
|
|
gpmc_irq_endis(p->irq, false);
|
|
}
|
|
|
|
static void gpmc_irq_enable(struct irq_data *p)
|
|
{
|
|
gpmc_irq_endis(p->irq, true);
|
|
}
|
|
|
|
static void gpmc_irq_noop(struct irq_data *data) { }
|
|
|
|
static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
|
|
|
|
static int gpmc_setup_irq(void)
|
|
{
|
|
int i;
|
|
u32 regval;
|
|
|
|
if (!gpmc_irq)
|
|
return -EINVAL;
|
|
|
|
gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
|
|
if (IS_ERR_VALUE(gpmc_irq_start)) {
|
|
pr_err("irq_alloc_descs failed\n");
|
|
return gpmc_irq_start;
|
|
}
|
|
|
|
gpmc_irq_chip.name = "gpmc";
|
|
gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
|
|
gpmc_irq_chip.irq_enable = gpmc_irq_enable;
|
|
gpmc_irq_chip.irq_disable = gpmc_irq_disable;
|
|
gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
|
|
gpmc_irq_chip.irq_ack = gpmc_irq_noop;
|
|
gpmc_irq_chip.irq_mask = gpmc_irq_noop;
|
|
gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
|
|
|
|
gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
|
|
gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
|
|
|
|
for (i = 0; i < GPMC_NR_IRQ; i++) {
|
|
gpmc_client_irq[i].irq = gpmc_irq_start + i;
|
|
irq_set_chip_and_handler(gpmc_client_irq[i].irq,
|
|
&gpmc_irq_chip, handle_simple_irq);
|
|
set_irq_flags(gpmc_client_irq[i].irq,
|
|
IRQF_VALID | IRQF_NOAUTOEN);
|
|
}
|
|
|
|
/* Disable interrupts */
|
|
gpmc_write_reg(GPMC_IRQENABLE, 0);
|
|
|
|
/* clear interrupts */
|
|
regval = gpmc_read_reg(GPMC_IRQSTATUS);
|
|
gpmc_write_reg(GPMC_IRQSTATUS, regval);
|
|
|
|
return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
|
|
}
|
|
|
|
static __devexit int gpmc_free_irq(void)
|
|
{
|
|
int i;
|
|
|
|
if (gpmc_irq)
|
|
free_irq(gpmc_irq, NULL);
|
|
|
|
for (i = 0; i < GPMC_NR_IRQ; i++) {
|
|
irq_set_handler(gpmc_client_irq[i].irq, NULL);
|
|
irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
|
|
irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
|
|
}
|
|
|
|
irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __devexit gpmc_mem_exit(void)
|
|
{
|
|
int cs;
|
|
|
|
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
|
|
if (!gpmc_cs_mem_enabled(cs))
|
|
continue;
|
|
gpmc_cs_delete_mem(cs);
|
|
}
|
|
|
|
}
|
|
|
|
static int __devinit gpmc_mem_init(void)
|
|
{
|
|
int cs, rc;
|
|
unsigned long boot_rom_space = 0;
|
|
|
|
/* never allocate the first page, to facilitate bug detection;
|
|
* even if we didn't boot from ROM.
|
|
*/
|
|
boot_rom_space = BOOT_ROM_SPACE;
|
|
/* In apollon the CS0 is mapped as 0x0000 0000 */
|
|
if (machine_is_omap_apollon())
|
|
boot_rom_space = 0;
|
|
gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
|
|
gpmc_mem_root.end = GPMC_MEM_END;
|
|
|
|
/* Reserve all regions that has been set up by bootloader */
|
|
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
|
|
u32 base, size;
|
|
|
|
if (!gpmc_cs_mem_enabled(cs))
|
|
continue;
|
|
gpmc_cs_get_memconf(cs, &base, &size);
|
|
rc = gpmc_cs_insert_mem(cs, base, size);
|
|
if (IS_ERR_VALUE(rc)) {
|
|
while (--cs >= 0)
|
|
if (gpmc_cs_mem_enabled(cs))
|
|
gpmc_cs_delete_mem(cs);
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __devinit int gpmc_probe(struct platform_device *pdev)
|
|
{
|
|
int rc;
|
|
u32 l;
|
|
struct resource *res;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (res == NULL)
|
|
return -ENOENT;
|
|
|
|
phys_base = res->start;
|
|
mem_size = resource_size(res);
|
|
|
|
gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
|
|
if (!gpmc_base) {
|
|
dev_err(&pdev->dev, "error: request memory / ioremap\n");
|
|
return -EADDRNOTAVAIL;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (res == NULL)
|
|
dev_warn(&pdev->dev, "Failed to get resource: irq\n");
|
|
else
|
|
gpmc_irq = res->start;
|
|
|
|
gpmc_l3_clk = clk_get(&pdev->dev, "fck");
|
|
if (IS_ERR(gpmc_l3_clk)) {
|
|
dev_err(&pdev->dev, "error: clk_get\n");
|
|
gpmc_irq = 0;
|
|
return PTR_ERR(gpmc_l3_clk);
|
|
}
|
|
|
|
clk_prepare_enable(gpmc_l3_clk);
|
|
|
|
gpmc_dev = &pdev->dev;
|
|
|
|
l = gpmc_read_reg(GPMC_REVISION);
|
|
if (GPMC_REVISION_MAJOR(l) > 0x4)
|
|
gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
|
|
dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
|
|
GPMC_REVISION_MINOR(l));
|
|
|
|
rc = gpmc_mem_init();
|
|
if (IS_ERR_VALUE(rc)) {
|
|
clk_disable_unprepare(gpmc_l3_clk);
|
|
clk_put(gpmc_l3_clk);
|
|
dev_err(gpmc_dev, "failed to reserve memory\n");
|
|
return rc;
|
|
}
|
|
|
|
if (IS_ERR_VALUE(gpmc_setup_irq()))
|
|
dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __devexit int gpmc_remove(struct platform_device *pdev)
|
|
{
|
|
gpmc_free_irq();
|
|
gpmc_mem_exit();
|
|
gpmc_dev = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver gpmc_driver = {
|
|
.probe = gpmc_probe,
|
|
.remove = __devexit_p(gpmc_remove),
|
|
.driver = {
|
|
.name = DEVICE_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static __init int gpmc_init(void)
|
|
{
|
|
return platform_driver_register(&gpmc_driver);
|
|
}
|
|
|
|
static __exit void gpmc_exit(void)
|
|
{
|
|
platform_driver_unregister(&gpmc_driver);
|
|
|
|
}
|
|
|
|
postcore_initcall(gpmc_init);
|
|
module_exit(gpmc_exit);
|
|
|
|
static int __init omap_gpmc_init(void)
|
|
{
|
|
struct omap_hwmod *oh;
|
|
struct platform_device *pdev;
|
|
char *oh_name = "gpmc";
|
|
|
|
oh = omap_hwmod_lookup(oh_name);
|
|
if (!oh) {
|
|
pr_err("Could not look up %s\n", oh_name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
|
|
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
|
|
|
|
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
|
|
}
|
|
postcore_initcall(omap_gpmc_init);
|
|
|
|
static irqreturn_t gpmc_handle_irq(int irq, void *dev)
|
|
{
|
|
int i;
|
|
u32 regval;
|
|
|
|
regval = gpmc_read_reg(GPMC_IRQSTATUS);
|
|
|
|
if (!regval)
|
|
return IRQ_NONE;
|
|
|
|
for (i = 0; i < GPMC_NR_IRQ; i++)
|
|
if (regval & gpmc_client_irq[i].bitmask)
|
|
generic_handle_irq(gpmc_client_irq[i].irq);
|
|
|
|
gpmc_write_reg(GPMC_IRQSTATUS, regval);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct omap3_gpmc_regs gpmc_context;
|
|
|
|
void omap3_gpmc_save_context(void)
|
|
{
|
|
int i;
|
|
|
|
gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
|
|
gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
|
|
gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
|
|
gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
|
|
gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
|
|
gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
|
|
gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
|
|
for (i = 0; i < GPMC_CS_NUM; i++) {
|
|
gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
|
|
if (gpmc_context.cs_context[i].is_valid) {
|
|
gpmc_context.cs_context[i].config1 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
|
|
gpmc_context.cs_context[i].config2 =
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gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
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gpmc_context.cs_context[i].config3 =
|
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gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
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gpmc_context.cs_context[i].config4 =
|
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gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
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gpmc_context.cs_context[i].config5 =
|
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gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
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|
gpmc_context.cs_context[i].config6 =
|
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gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
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|
gpmc_context.cs_context[i].config7 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
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|
}
|
|
}
|
|
}
|
|
|
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void omap3_gpmc_restore_context(void)
|
|
{
|
|
int i;
|
|
|
|
gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
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|
gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
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|
gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
|
|
gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
|
|
gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
|
|
gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
|
|
gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
|
|
for (i = 0; i < GPMC_CS_NUM; i++) {
|
|
if (gpmc_context.cs_context[i].is_valid) {
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
|
|
gpmc_context.cs_context[i].config1);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
|
|
gpmc_context.cs_context[i].config2);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
|
|
gpmc_context.cs_context[i].config3);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
|
|
gpmc_context.cs_context[i].config4);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
|
|
gpmc_context.cs_context[i].config5);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
|
|
gpmc_context.cs_context[i].config6);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
|
|
gpmc_context.cs_context[i].config7);
|
|
}
|
|
}
|
|
}
|
|
#endif /* CONFIG_ARCH_OMAP3 */
|