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c78275f366
The eTSEC includes a PTP clock with quite a few features. This patch adds support for the basic clock adjustment functions, plus two external time stamps, one alarm, and the PPS callback. Signed-off-by: Richard Cochran <richard.cochran@omicron.at> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: John Stultz <john.stultz@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org>
131 lines
4.9 KiB
Plaintext
131 lines
4.9 KiB
Plaintext
* MDIO IO device
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The MDIO is a bus to which the PHY devices are connected. For each
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device that exists on this bus, a child node should be created. See
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the definition of the PHY node in booting-without-of.txt for an example
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of how to define a PHY.
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Required properties:
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- reg : Offset and length of the register set for the device
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- compatible : Should define the compatible device type for the
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mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
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Example:
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mdio@24520 {
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reg = <24520 20>;
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compatible = "fsl,gianfar-mdio";
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ethernet-phy@0 {
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......
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};
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};
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* TBI Internal MDIO bus
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As of this writing, every tsec is associated with an internal TBI PHY.
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This PHY is accessed through the local MDIO bus. These buses are defined
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similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
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The TBI PHYs underneath them are similar to normal PHYs, but the reg property
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is considered instructive, rather than descriptive. The reg property should
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be chosen so it doesn't interfere with other PHYs on the bus.
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* Gianfar-compatible ethernet nodes
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Properties:
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- device_type : Should be "network"
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- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
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- compatible : Should be "gianfar"
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- reg : Offset and length of the register set for the device
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- local-mac-address : List of bytes representing the ethernet address of
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this controller
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- interrupts : For FEC devices, the first interrupt is the device's
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interrupt. For TSEC and eTSEC devices, the first interrupt is
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transmit, the second is receive, and the third is error.
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- phy-handle : The phandle for the PHY connected to this ethernet
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controller.
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- fixed-link : <a b c d e> where a is emulated phy id - choose any,
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but unique to the all specified fixed-links, b is duplex - 0 half,
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1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
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pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
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- phy-connection-type : a string naming the controller/PHY interface type,
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i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
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"tbi", or "rtbi". This property is only really needed if the connection
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is of type "rgmii-id", as all other connection types are detected by
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hardware.
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- fsl,magic-packet : If present, indicates that the hardware supports
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waking up via magic packet.
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- bd-stash : If present, indicates that the hardware supports stashing
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buffer descriptors in the L2.
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- rx-stash-len : Denotes the number of bytes of a received buffer to stash
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in the L2.
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- rx-stash-idx : Denotes the index of the first byte from the received
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buffer to stash in the L2.
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Example:
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ethernet@24000 {
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 E0 0C 00 73 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>
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};
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* Gianfar PTP clock nodes
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General Properties:
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- compatible Should be "fsl,etsec-ptp"
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- reg Offset and length of the register set for the device
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- interrupts There should be at least two interrupts. Some devices
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have as many as four PTP related interrupts.
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Clock Properties:
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- fsl,tclk-period Timer reference clock period in nanoseconds.
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- fsl,tmr-prsc Prescaler, divides the output clock.
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- fsl,tmr-add Frequency compensation value.
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- fsl,tmr-fiper1 Fixed interval period pulse generator.
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- fsl,tmr-fiper2 Fixed interval period pulse generator.
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- fsl,max-adj Maximum frequency adjustment in parts per billion.
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These properties set the operational parameters for the PTP
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clock. You must choose these carefully for the clock to work right.
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Here is how to figure good values:
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TimerOsc = system clock MHz
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tclk_period = desired clock period nanoseconds
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NominalFreq = 1000 / tclk_period MHz
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FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
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tmr_add = ceil(2^32 / FreqDivRatio)
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OutputClock = NominalFreq / tmr_prsc MHz
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PulseWidth = 1 / OutputClock microseconds
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FiperFreq1 = desired frequency in Hz
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FiperDiv1 = 1000000 * OutputClock / FiperFreq1
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tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
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max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
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The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
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driver expects that tmr_fiper1 will be correctly set to produce a 1
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Pulse Per Second (PPS) signal, since this will be offered to the PPS
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subsystem to synchronize the Linux clock.
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Example:
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ptp_clock@24E00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <12 0x8 13 0x8>;
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interrupt-parent = < &ipic >;
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fsl,tclk-period = <10>;
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fsl,tmr-prsc = <100>;
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fsl,tmr-add = <0x999999A4>;
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fsl,tmr-fiper1 = <0x3B9AC9F6>;
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fsl,tmr-fiper2 = <0x00018696>;
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fsl,max-adj = <659999998>;
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};
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