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687e3d5550
As of_get_mac_address now supports NVMEM under the hood, we need to update the bindings documentation with the new nvmem-cell* properties, which would mean copy&pasting a lot of redundant information to every binding documentation currently referencing some of the MAC address properties. So I've just removed all the references to the optional MAC address properties and replaced them with the small note referencing net/ethernet.txt file. Signed-off-by: Petr Štetiar <ynezz@true.cz> Signed-off-by: David S. Miller <davem@davemloft.net>
77 lines
2.9 KiB
Plaintext
77 lines
2.9 KiB
Plaintext
* AMD 10GbE driver (amd-xgbe)
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Required properties:
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- compatible: Should be "amd,xgbe-seattle-v1a"
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- reg: Address and length of the register sets for the device
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- MAC registers
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- PCS registers
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- SerDes Rx/Tx registers
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- SerDes integration registers (1/2)
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- SerDes integration registers (2/2)
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- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
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listed is required and is the general device interrupt. If the optional
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amd,per-channel-interrupt property is specified, then one additional
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interrupt for each DMA channel supported by the device should be specified.
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The last interrupt listed should be the PCS auto-negotiation interrupt.
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- clocks:
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- DMA clock for the amd-xgbe device (used for calculating the
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correct Rx interrupt watchdog timer value on a DMA channel
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for coalescing)
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- PTP clock for the amd-xgbe device
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- clock-names: Should be the names of the clocks
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- "dma_clk" for the DMA clock
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- "ptp_clk" for the PTP clock
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- phy-mode: See ethernet.txt file in the same directory
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Optional properties:
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- dma-coherent: Present if dma operations are coherent
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- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
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a unique interrupt for each DMA channel - this requires an additional
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interrupt be configured for each DMA channel
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- amd,speed-set: Speed capabilities of the device
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0 - 1GbE and 10GbE (default)
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1 - 2.5GbE and 10GbE
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The MAC address will be determined using the optional properties defined in
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ethernet.txt.
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The following optional properties are represented by an array with each
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value corresponding to a particular speed. The first array value represents
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the setting for the 1GbE speed, the second value for the 2.5GbE speed and
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the third value for the 10GbE speed. All three values are required if the
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property is used.
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- amd,serdes-blwc: Baseline wandering correction enablement
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0 - Off
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1 - On
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- amd,serdes-cdr-rate: CDR rate speed selection
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- amd,serdes-pq-skew: PQ (data sampling) skew
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- amd,serdes-tx-amp: TX amplitude boost
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- amd,serdes-dfe-tap-config: DFE taps available to run
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- amd,serdes-dfe-tap-enable: DFE taps to enable
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Example:
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xgbe@e0700000 {
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compatible = "amd,xgbe-seattle-v1a";
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reg = <0 0xe0700000 0 0x80000>,
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<0 0xe0780000 0 0x80000>,
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<0 0xe1240800 0 0x00400>,
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<0 0xe1250000 0 0x00060>,
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<0 0xe1250080 0 0x00004>;
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interrupt-parent = <&gic>;
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interrupts = <0 325 4>,
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<0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
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<0 323 4>;
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amd,per-channel-interrupt;
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clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
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clock-names = "dma_clk", "ptp_clk";
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phy-mode = "xgmii";
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mac-address = [ 02 a1 a2 a3 a4 a5 ];
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amd,speed-set = <0>;
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amd,serdes-blwc = <1>, <1>, <0>;
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amd,serdes-cdr-rate = <2>, <2>, <7>;
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amd,serdes-pq-skew = <10>, <10>, <30>;
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amd,serdes-tx-amp = <15>, <15>, <10>;
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amd,serdes-dfe-tap-config = <3>, <3>, <1>;
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amd,serdes-dfe-tap-enable = <0>, <0>, <127>;
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};
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