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b5466f8728
ASIDs are allocated to MMU contexts based on a rolling counter. This means that after 255 allocations we must invalidate all existing ASIDs via an expensive IPI mechanism to synchronise all of the online CPUs and ensure that all tasks execute with an ASID from the new generation. This patch changes the rollover behaviour so that we rely instead on the hardware broadcasting of the TLB invalidation to avoid the IPI calls. This works by keeping track of the active ASID on each core, which is then reserved in the case of a rollover so that currently scheduled tasks can continue to run. For cores without hardware TLB broadcasting, we keep track of pending flushes in a cpumask, so cores can flush their local TLB before scheduling a new mm. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
35 lines
561 B
C
35 lines
561 B
C
#ifndef __ARM_MMU_H
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#define __ARM_MMU_H
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#ifdef CONFIG_MMU
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typedef struct {
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#ifdef CONFIG_CPU_HAS_ASID
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u64 id;
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#endif
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unsigned int kvm_seq;
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} mm_context_t;
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#ifdef CONFIG_CPU_HAS_ASID
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#define ASID_BITS 8
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#define ASID_MASK ((~0ULL) << ASID_BITS)
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#define ASID(mm) ((mm)->context.id & ~ASID_MASK)
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#else
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#define ASID(mm) (0)
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#endif
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#else
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/*
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* From nommu.h:
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* Copyright (C) 2002, David McCullough <davidm@snapgear.com>
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* modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
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*/
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typedef struct {
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unsigned long end_brk;
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} mm_context_t;
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#endif
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#endif
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