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22043a3c08
To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be disabled. To take maximum advantage of the hardware, the full available vector length also needs to be enabled for EL1 by programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as required, but this cannot override the limit set by ZCR_EL2.) This patch makes the appropriate changes to the EL2 early setup code. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
773 lines
21 KiB
ArmAsm
773 lines
21 KiB
ArmAsm
/*
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* Low-level CPU initialisation
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* Based on arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (C) 2003-2012 ARM Ltd.
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* Authors: Catalin Marinas <catalin.marinas@arm.com>
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* Will Deacon <will.deacon@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/assembler.h>
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#include <asm/boot.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/cputype.h>
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#include <asm/elf.h>
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#include <asm/kernel-pgtable.h>
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#include <asm/kvm_arm.h>
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#include <asm/memory.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/smp.h>
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#include <asm/sysreg.h>
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#include <asm/thread_info.h>
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#include <asm/virt.h>
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#include "efi-header.S"
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#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
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#if (TEXT_OFFSET & 0xfff) != 0
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#error TEXT_OFFSET must be at least 4KB aligned
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#elif (PAGE_OFFSET & 0x1fffff) != 0
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#error PAGE_OFFSET must be at least 2MB aligned
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#elif TEXT_OFFSET > 0x1fffff
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#error TEXT_OFFSET must be less than 2MB
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* The requirements are:
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* MMU = off, D-cache = off, I-cache = on or off,
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* x0 = physical address to the FDT blob.
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*
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* This code is mostly position independent so you call this at
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* __pa(PAGE_OFFSET + TEXT_OFFSET).
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*
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* Note that the callee-saved registers are used for storing variables
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* that are useful before the MMU is enabled. The allocations are described
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* in the entry routines.
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*/
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__HEAD
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_head:
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/*
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* DO NOT MODIFY. Image header expected by Linux boot-loaders.
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*/
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#ifdef CONFIG_EFI
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/*
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* This add instruction has no meaningful effect except that
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* its opcode forms the magic "MZ" signature required by UEFI.
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*/
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add x13, x18, #0x16
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b stext
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#else
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b stext // branch to kernel start, magic
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.long 0 // reserved
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#endif
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le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
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le64sym _kernel_size_le // Effective size of kernel image, little-endian
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le64sym _kernel_flags_le // Informative flags, little-endian
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.quad 0 // reserved
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.quad 0 // reserved
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.quad 0 // reserved
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.ascii "ARM\x64" // Magic number
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#ifdef CONFIG_EFI
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.long pe_header - _head // Offset to the PE header.
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pe_header:
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__EFI_PE_HEADER
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#else
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.long 0 // reserved
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#endif
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__INIT
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/*
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* The following callee saved general purpose registers are used on the
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* primary lowlevel boot path:
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*
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* Register Scope Purpose
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* x21 stext() .. start_kernel() FDT pointer passed at boot in x0
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* x23 stext() .. start_kernel() physical misalignment/KASLR offset
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* x28 __create_page_tables() callee preserved temp register
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* x19/x20 __primary_switch() callee preserved temp registers
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*/
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ENTRY(stext)
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bl preserve_boot_args
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bl el2_setup // Drop to EL1, w0=cpu_boot_mode
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adrp x23, __PHYS_OFFSET
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and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
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bl set_cpu_boot_mode_flag
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bl __create_page_tables
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/*
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* The following calls CPU setup code, see arch/arm64/mm/proc.S for
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* details.
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* On return, the CPU will be ready for the MMU to be turned on and
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* the TCR will have been set.
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*/
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bl __cpu_setup // initialise processor
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b __primary_switch
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ENDPROC(stext)
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/*
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* Preserve the arguments passed by the bootloader in x0 .. x3
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*/
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preserve_boot_args:
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mov x21, x0 // x21=FDT
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adr_l x0, boot_args // record the contents of
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stp x21, x1, [x0] // x0 .. x3 at kernel entry
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stp x2, x3, [x0, #16]
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dmb sy // needed before dc ivac with
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// MMU off
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mov x1, #0x20 // 4 x 8 bytes
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b __inval_dcache_area // tail call
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ENDPROC(preserve_boot_args)
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/*
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* Macro to create a table entry to the next page.
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*
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* tbl: page table address
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* virt: virtual address
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* shift: #imm page table shift
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* ptrs: #imm pointers per table page
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*
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* Preserves: virt
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* Corrupts: tmp1, tmp2
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* Returns: tbl -> next level table page address
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*/
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.macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
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lsr \tmp1, \virt, #\shift
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and \tmp1, \tmp1, #\ptrs - 1 // table index
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add \tmp2, \tbl, #PAGE_SIZE
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orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
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str \tmp2, [\tbl, \tmp1, lsl #3]
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add \tbl, \tbl, #PAGE_SIZE // next level table page
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.endm
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/*
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* Macro to populate the PGD (and possibily PUD) for the corresponding
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* block entry in the next level (tbl) for the given virtual address.
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*
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* Preserves: tbl, next, virt
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* Corrupts: tmp1, tmp2
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*/
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.macro create_pgd_entry, tbl, virt, tmp1, tmp2
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create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
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#if SWAPPER_PGTABLE_LEVELS > 3
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create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
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#endif
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#if SWAPPER_PGTABLE_LEVELS > 2
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create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
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#endif
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.endm
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/*
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* Macro to populate block entries in the page table for the start..end
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* virtual range (inclusive).
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*
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* Preserves: tbl, flags
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* Corrupts: phys, start, end, pstate
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*/
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.macro create_block_map, tbl, flags, phys, start, end
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lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
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lsr \start, \start, #SWAPPER_BLOCK_SHIFT
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and \start, \start, #PTRS_PER_PTE - 1 // table index
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orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
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lsr \end, \end, #SWAPPER_BLOCK_SHIFT
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and \end, \end, #PTRS_PER_PTE - 1 // table end index
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9999: str \phys, [\tbl, \start, lsl #3] // store the entry
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add \start, \start, #1 // next entry
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add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
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cmp \start, \end
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b.ls 9999b
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.endm
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/*
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* Setup the initial page tables. We only setup the barest amount which is
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* required to get the kernel running. The following sections are required:
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* - identity mapping to enable the MMU (low address, TTBR0)
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* - first few MB of the kernel linear mapping to jump to once the MMU has
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* been enabled
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*/
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__create_page_tables:
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mov x28, lr
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/*
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* Invalidate the idmap and swapper page tables to avoid potential
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* dirty cache lines being evicted.
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*/
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adrp x0, idmap_pg_dir
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ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
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bl __inval_dcache_area
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/*
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* Clear the idmap and swapper page tables.
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*/
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adrp x0, idmap_pg_dir
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ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
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1: stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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subs x1, x1, #64
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b.ne 1b
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mov x7, SWAPPER_MM_MMUFLAGS
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/*
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* Create the identity mapping.
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*/
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adrp x0, idmap_pg_dir
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adrp x3, __idmap_text_start // __pa(__idmap_text_start)
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#ifndef CONFIG_ARM64_VA_BITS_48
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#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
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#define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
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/*
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* If VA_BITS < 48, it may be too small to allow for an ID mapping to be
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* created that covers system RAM if that is located sufficiently high
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* in the physical address space. So for the ID map, use an extended
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* virtual range in that case, by configuring an additional translation
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* level.
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* First, we have to verify our assumption that the current value of
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* VA_BITS was chosen such that all translation levels are fully
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* utilised, and that lowering T0SZ will always result in an additional
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* translation level to be configured.
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*/
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#if VA_BITS != EXTRA_SHIFT
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#error "Mismatch between VA_BITS and page size/number of translation levels"
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#endif
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/*
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* Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
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* entire ID map region can be mapped. As T0SZ == (64 - #bits used),
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* this number conveniently equals the number of leading zeroes in
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* the physical address of __idmap_text_end.
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*/
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adrp x5, __idmap_text_end
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clz x5, x5
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cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
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b.ge 1f // .. then skip additional level
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adr_l x6, idmap_t0sz
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str x5, [x6]
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dmb sy
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dc ivac, x6 // Invalidate potentially stale cache line
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create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
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1:
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#endif
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create_pgd_entry x0, x3, x5, x6
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mov x5, x3 // __pa(__idmap_text_start)
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adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
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create_block_map x0, x7, x3, x5, x6
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/*
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* Map the kernel image (starting with PHYS_OFFSET).
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*/
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adrp x0, swapper_pg_dir
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mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
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add x5, x5, x23 // add KASLR displacement
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create_pgd_entry x0, x5, x3, x6
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adrp x6, _end // runtime __pa(_end)
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adrp x3, _text // runtime __pa(_text)
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sub x6, x6, x3 // _end - _text
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add x6, x6, x5 // runtime __va(_end)
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create_block_map x0, x7, x3, x5, x6
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/*
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* Since the page tables have been populated with non-cacheable
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* accesses (MMU disabled), invalidate the idmap and swapper page
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* tables again to remove any speculatively loaded cache lines.
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*/
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adrp x0, idmap_pg_dir
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ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
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dmb sy
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bl __inval_dcache_area
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ret x28
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ENDPROC(__create_page_tables)
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.ltorg
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/*
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* The following fragment of code is executed with the MMU enabled.
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*
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* x0 = __PHYS_OFFSET
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*/
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__primary_switched:
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adrp x4, init_thread_union
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add sp, x4, #THREAD_SIZE
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adr_l x5, init_task
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msr sp_el0, x5 // Save thread_info
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adr_l x8, vectors // load VBAR_EL1 with virtual
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msr vbar_el1, x8 // vector table address
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isb
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stp xzr, x30, [sp, #-16]!
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mov x29, sp
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str_l x21, __fdt_pointer, x5 // Save FDT pointer
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ldr_l x4, kimage_vaddr // Save the offset between
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sub x4, x4, x0 // the kernel virtual and
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str_l x4, kimage_voffset, x5 // physical mappings
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// Clear BSS
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adr_l x0, __bss_start
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mov x1, xzr
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adr_l x2, __bss_stop
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sub x2, x2, x0
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bl __pi_memset
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dsb ishst // Make zero page visible to PTW
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#ifdef CONFIG_KASAN
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bl kasan_early_init
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#endif
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#ifdef CONFIG_RANDOMIZE_BASE
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tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
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b.ne 0f
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mov x0, x21 // pass FDT address in x0
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bl kaslr_early_init // parse FDT for KASLR options
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cbz x0, 0f // KASLR disabled? just proceed
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orr x23, x23, x0 // record KASLR offset
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ldp x29, x30, [sp], #16 // we must enable KASLR, return
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ret // to __primary_switch()
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0:
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#endif
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add sp, sp, #16
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mov x29, #0
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mov x30, #0
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b start_kernel
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ENDPROC(__primary_switched)
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/*
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* end early head section, begin head code that is also used for
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* hotplug and needs to have the same protections as the text region
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*/
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.section ".idmap.text","ax"
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ENTRY(kimage_vaddr)
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.quad _text - TEXT_OFFSET
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/*
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* If we're fortunate enough to boot at EL2, ensure that the world is
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* sane before dropping to EL1.
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*
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* Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
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* booted in EL1 or EL2 respectively.
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*/
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ENTRY(el2_setup)
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msr SPsel, #1 // We want to use SP_EL{1,2}
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL2
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b.eq 1f
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mrs x0, sctlr_el1
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CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
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CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
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msr sctlr_el1, x0
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mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
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isb
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ret
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1: mrs x0, sctlr_el2
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CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
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CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
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msr sctlr_el2, x0
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#ifdef CONFIG_ARM64_VHE
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/*
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* Check for VHE being present. For the rest of the EL2 setup,
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* x2 being non-zero indicates that we do have VHE, and that the
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* kernel is intended to run at EL2.
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*/
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mrs x2, id_aa64mmfr1_el1
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ubfx x2, x2, #8, #4
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#else
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mov x2, xzr
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#endif
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/* Hyp configuration. */
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mov x0, #HCR_RW // 64-bit EL1
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cbz x2, set_hcr
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orr x0, x0, #HCR_TGE // Enable Host Extensions
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orr x0, x0, #HCR_E2H
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set_hcr:
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msr hcr_el2, x0
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isb
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/*
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* Allow Non-secure EL1 and EL0 to access physical timer and counter.
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* This is not necessary for VHE, since the host kernel runs in EL2,
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* and EL0 accesses are configured in the later stage of boot process.
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* Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
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* as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
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* to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
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* to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
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* EL2.
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*/
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cbnz x2, 1f
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mrs x0, cnthctl_el2
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orr x0, x0, #3 // Enable EL1 physical timers
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msr cnthctl_el2, x0
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1:
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msr cntvoff_el2, xzr // Clear virtual offset
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#ifdef CONFIG_ARM_GIC_V3
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/* GICv3 system register access */
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #24, #4
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cmp x0, #1
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b.ne 3f
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mrs_s x0, SYS_ICC_SRE_EL2
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orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
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orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
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msr_s SYS_ICC_SRE_EL2, x0
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isb // Make sure SRE is now set
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mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
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tbz x0, #0, 3f // and check that it sticks
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msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
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3:
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#endif
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/* Populate ID registers. */
|
|
mrs x0, midr_el1
|
|
mrs x1, mpidr_el1
|
|
msr vpidr_el2, x0
|
|
msr vmpidr_el2, x1
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
msr hstr_el2, xzr // Disable CP15 traps to EL2
|
|
#endif
|
|
|
|
/* EL2 debug */
|
|
mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
|
|
sbfx x0, x1, #8, #4
|
|
cmp x0, #1
|
|
b.lt 4f // Skip if no PMU present
|
|
mrs x0, pmcr_el0 // Disable debug access traps
|
|
ubfx x0, x0, #11, #5 // to EL2 and allow access to
|
|
4:
|
|
csel x3, xzr, x0, lt // all PMU counters from EL1
|
|
|
|
/* Statistical profiling */
|
|
ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer
|
|
cbz x0, 7f // Skip if SPE not present
|
|
cbnz x2, 6f // VHE?
|
|
mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2,
|
|
and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
|
|
cbnz x4, 5f // then permit sampling of physical
|
|
mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
|
|
1 << SYS_PMSCR_EL2_PA_SHIFT)
|
|
msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter
|
|
5:
|
|
mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
|
|
orr x3, x3, x1 // If we don't have VHE, then
|
|
b 7f // use EL1&0 translation.
|
|
6: // For VHE, use EL2 translation
|
|
orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1
|
|
7:
|
|
msr mdcr_el2, x3 // Configure debug traps
|
|
|
|
/* Stage-2 translation */
|
|
msr vttbr_el2, xzr
|
|
|
|
cbz x2, install_el2_stub
|
|
|
|
mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
|
|
isb
|
|
ret
|
|
|
|
install_el2_stub:
|
|
/*
|
|
* When VHE is not in use, early init of EL2 and EL1 needs to be
|
|
* done here.
|
|
* When VHE _is_ in use, EL1 will not be used in the host and
|
|
* requires no configuration, and all non-hyp-specific EL2 setup
|
|
* will be done via the _EL1 system register aliases in __cpu_setup.
|
|
*/
|
|
/* sctlr_el1 */
|
|
mov x0, #0x0800 // Set/clear RES{1,0} bits
|
|
CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
|
|
CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
|
|
msr sctlr_el1, x0
|
|
|
|
/* Coprocessor traps. */
|
|
mov x0, #0x33ff
|
|
msr cptr_el2, x0 // Disable copro. traps to EL2
|
|
|
|
/* SVE register access */
|
|
mrs x1, id_aa64pfr0_el1
|
|
ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
|
|
cbz x1, 7f
|
|
|
|
bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
|
|
msr cptr_el2, x0 // Disable copro. traps to EL2
|
|
isb
|
|
mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
|
|
msr_s SYS_ZCR_EL2, x1 // length for EL1.
|
|
|
|
/* Hypervisor stub */
|
|
7: adr_l x0, __hyp_stub_vectors
|
|
msr vbar_el2, x0
|
|
|
|
/* spsr */
|
|
mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
|
|
PSR_MODE_EL1h)
|
|
msr spsr_el2, x0
|
|
msr elr_el2, lr
|
|
mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
|
|
eret
|
|
ENDPROC(el2_setup)
|
|
|
|
/*
|
|
* Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
|
|
* in w0. See arch/arm64/include/asm/virt.h for more info.
|
|
*/
|
|
set_cpu_boot_mode_flag:
|
|
adr_l x1, __boot_cpu_mode
|
|
cmp w0, #BOOT_CPU_MODE_EL2
|
|
b.ne 1f
|
|
add x1, x1, #4
|
|
1: str w0, [x1] // This CPU has booted in EL1
|
|
dmb sy
|
|
dc ivac, x1 // Invalidate potentially stale cache line
|
|
ret
|
|
ENDPROC(set_cpu_boot_mode_flag)
|
|
|
|
/*
|
|
* These values are written with the MMU off, but read with the MMU on.
|
|
* Writers will invalidate the corresponding address, discarding up to a
|
|
* 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
|
|
* sufficient alignment that the CWG doesn't overlap another section.
|
|
*/
|
|
.pushsection ".mmuoff.data.write", "aw"
|
|
/*
|
|
* We need to find out the CPU boot mode long after boot, so we need to
|
|
* store it in a writable variable.
|
|
*
|
|
* This is not in .bss, because we set it sufficiently early that the boot-time
|
|
* zeroing of .bss would clobber it.
|
|
*/
|
|
ENTRY(__boot_cpu_mode)
|
|
.long BOOT_CPU_MODE_EL2
|
|
.long BOOT_CPU_MODE_EL1
|
|
/*
|
|
* The booting CPU updates the failed status @__early_cpu_boot_status,
|
|
* with MMU turned off.
|
|
*/
|
|
ENTRY(__early_cpu_boot_status)
|
|
.long 0
|
|
|
|
.popsection
|
|
|
|
/*
|
|
* This provides a "holding pen" for platforms to hold all secondary
|
|
* cores are held until we're ready for them to initialise.
|
|
*/
|
|
ENTRY(secondary_holding_pen)
|
|
bl el2_setup // Drop to EL1, w0=cpu_boot_mode
|
|
bl set_cpu_boot_mode_flag
|
|
mrs x0, mpidr_el1
|
|
mov_q x1, MPIDR_HWID_BITMASK
|
|
and x0, x0, x1
|
|
adr_l x3, secondary_holding_pen_release
|
|
pen: ldr x4, [x3]
|
|
cmp x4, x0
|
|
b.eq secondary_startup
|
|
wfe
|
|
b pen
|
|
ENDPROC(secondary_holding_pen)
|
|
|
|
/*
|
|
* Secondary entry point that jumps straight into the kernel. Only to
|
|
* be used where CPUs are brought online dynamically by the kernel.
|
|
*/
|
|
ENTRY(secondary_entry)
|
|
bl el2_setup // Drop to EL1
|
|
bl set_cpu_boot_mode_flag
|
|
b secondary_startup
|
|
ENDPROC(secondary_entry)
|
|
|
|
secondary_startup:
|
|
/*
|
|
* Common entry point for secondary CPUs.
|
|
*/
|
|
bl __cpu_setup // initialise processor
|
|
bl __enable_mmu
|
|
ldr x8, =__secondary_switched
|
|
br x8
|
|
ENDPROC(secondary_startup)
|
|
|
|
__secondary_switched:
|
|
adr_l x5, vectors
|
|
msr vbar_el1, x5
|
|
isb
|
|
|
|
adr_l x0, secondary_data
|
|
ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
|
|
mov sp, x1
|
|
ldr x2, [x0, #CPU_BOOT_TASK]
|
|
msr sp_el0, x2
|
|
mov x29, #0
|
|
mov x30, #0
|
|
b secondary_start_kernel
|
|
ENDPROC(__secondary_switched)
|
|
|
|
/*
|
|
* The booting CPU updates the failed status @__early_cpu_boot_status,
|
|
* with MMU turned off.
|
|
*
|
|
* update_early_cpu_boot_status tmp, status
|
|
* - Corrupts tmp1, tmp2
|
|
* - Writes 'status' to __early_cpu_boot_status and makes sure
|
|
* it is committed to memory.
|
|
*/
|
|
|
|
.macro update_early_cpu_boot_status status, tmp1, tmp2
|
|
mov \tmp2, #\status
|
|
adr_l \tmp1, __early_cpu_boot_status
|
|
str \tmp2, [\tmp1]
|
|
dmb sy
|
|
dc ivac, \tmp1 // Invalidate potentially stale cache line
|
|
.endm
|
|
|
|
/*
|
|
* Enable the MMU.
|
|
*
|
|
* x0 = SCTLR_EL1 value for turning on the MMU.
|
|
*
|
|
* Returns to the caller via x30/lr. This requires the caller to be covered
|
|
* by the .idmap.text section.
|
|
*
|
|
* Checks if the selected granule size is supported by the CPU.
|
|
* If it isn't, park the CPU
|
|
*/
|
|
ENTRY(__enable_mmu)
|
|
mrs x1, ID_AA64MMFR0_EL1
|
|
ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
|
|
cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
|
|
b.ne __no_granule_support
|
|
update_early_cpu_boot_status 0, x1, x2
|
|
adrp x1, idmap_pg_dir
|
|
adrp x2, swapper_pg_dir
|
|
msr ttbr0_el1, x1 // load TTBR0
|
|
msr ttbr1_el1, x2 // load TTBR1
|
|
isb
|
|
msr sctlr_el1, x0
|
|
isb
|
|
/*
|
|
* Invalidate the local I-cache so that any instructions fetched
|
|
* speculatively from the PoC are discarded, since they may have
|
|
* been dynamically patched at the PoU.
|
|
*/
|
|
ic iallu
|
|
dsb nsh
|
|
isb
|
|
ret
|
|
ENDPROC(__enable_mmu)
|
|
|
|
__no_granule_support:
|
|
/* Indicate that this CPU can't boot and is stuck in the kernel */
|
|
update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2
|
|
1:
|
|
wfe
|
|
wfi
|
|
b 1b
|
|
ENDPROC(__no_granule_support)
|
|
|
|
#ifdef CONFIG_RELOCATABLE
|
|
__relocate_kernel:
|
|
/*
|
|
* Iterate over each entry in the relocation table, and apply the
|
|
* relocations in place.
|
|
*/
|
|
ldr w9, =__rela_offset // offset to reloc table
|
|
ldr w10, =__rela_size // size of reloc table
|
|
|
|
mov_q x11, KIMAGE_VADDR // default virtual offset
|
|
add x11, x11, x23 // actual virtual offset
|
|
add x9, x9, x11 // __va(.rela)
|
|
add x10, x9, x10 // __va(.rela) + sizeof(.rela)
|
|
|
|
0: cmp x9, x10
|
|
b.hs 1f
|
|
ldp x11, x12, [x9], #24
|
|
ldr x13, [x9, #-8]
|
|
cmp w12, #R_AARCH64_RELATIVE
|
|
b.ne 0b
|
|
add x13, x13, x23 // relocate
|
|
str x13, [x11, x23]
|
|
b 0b
|
|
1: ret
|
|
ENDPROC(__relocate_kernel)
|
|
#endif
|
|
|
|
__primary_switch:
|
|
#ifdef CONFIG_RANDOMIZE_BASE
|
|
mov x19, x0 // preserve new SCTLR_EL1 value
|
|
mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
|
|
#endif
|
|
|
|
bl __enable_mmu
|
|
#ifdef CONFIG_RELOCATABLE
|
|
bl __relocate_kernel
|
|
#ifdef CONFIG_RANDOMIZE_BASE
|
|
ldr x8, =__primary_switched
|
|
adrp x0, __PHYS_OFFSET
|
|
blr x8
|
|
|
|
/*
|
|
* If we return here, we have a KASLR displacement in x23 which we need
|
|
* to take into account by discarding the current kernel mapping and
|
|
* creating a new one.
|
|
*/
|
|
msr sctlr_el1, x20 // disable the MMU
|
|
isb
|
|
bl __create_page_tables // recreate kernel mapping
|
|
|
|
tlbi vmalle1 // Remove any stale TLB entries
|
|
dsb nsh
|
|
|
|
msr sctlr_el1, x19 // re-enable the MMU
|
|
isb
|
|
ic iallu // flush instructions fetched
|
|
dsb nsh // via old mapping
|
|
isb
|
|
|
|
bl __relocate_kernel
|
|
#endif
|
|
#endif
|
|
ldr x8, =__primary_switched
|
|
adrp x0, __PHYS_OFFSET
|
|
br x8
|
|
ENDPROC(__primary_switch)
|