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0b4eb462da
Aligning the .bss section makes it trivial to use large operation sizes for moving the initialized sections and clearing the .bss. The alignment chosen (L1 cache) is somewhat arbitrary, but should be large enough to avoid all known performance traps and small enough to not cause troubles. [ Impact: trivial performance enhancement, future patch prep ] Signed-off-by: H. Peter Anvin <hpa@zytor.com>
61 lines
901 B
ArmAsm
61 lines
901 B
ArmAsm
OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT)
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#undef i386
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#ifdef CONFIG_X86_64
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OUTPUT_ARCH(i386:x86-64)
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ENTRY(startup_64)
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#else
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OUTPUT_ARCH(i386)
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ENTRY(startup_32)
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#endif
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SECTIONS
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{
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/* Be careful parts of head_64.S assume startup_32 is at
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* address 0.
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*/
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. = 0;
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.text.head : {
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_head = . ;
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*(.text.head)
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_ehead = . ;
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}
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.rodata.compressed : {
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*(.rodata.compressed)
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}
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.text : {
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_text = .; /* Text */
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*(.text)
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*(.text.*)
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_etext = . ;
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}
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.rodata : {
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_rodata = . ;
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*(.rodata) /* read-only data */
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*(.rodata.*)
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_erodata = . ;
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}
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.data : {
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_data = . ;
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*(.data)
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*(.data.*)
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_edata = . ;
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}
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. = ALIGN(CONFIG_X86_L1_CACHE_BYTES);
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.bss : {
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_bss = . ;
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*(.bss)
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*(.bss.*)
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*(COMMON)
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#ifdef CONFIG_X86_64
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. = ALIGN(8);
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_end_before_pgt = . ;
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. = ALIGN(4096);
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pgtable = . ;
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. = . + 4096 * 6;
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#endif
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_ebss = .;
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}
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}
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