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b3d75b09bf
__flush_cache_all for m54xx is intrinsically related to the bit definitions in m54xxacr.h. Move it there from cacheflush_no.h, for easier maintenance. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
75 lines
2.5 KiB
C
75 lines
2.5 KiB
C
/*
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* Bit definitions for the MCF54xx ACR and CACR registers.
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*/
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#ifndef m54xxacr_h
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#define m54xxacr_h
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/*
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* Define the Cache register flags.
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*/
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#define CACR_DEC 0x80000000 /* Enable data cache */
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#define CACR_DWP 0x40000000 /* Data write protection */
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#define CACR_DESB 0x20000000 /* Enable data store buffer */
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#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
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#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
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#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
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#define CACR_DDCM_P 0x04000000 /* No cache, precise */
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#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
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#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
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#define CACR_BEC 0x00080000 /* Enable branch cache */
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#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
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#define CACR_IEC 0x00008000 /* Enable instruction cache */
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#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
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#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
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#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
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#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
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#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
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#define ACR_BASE_POS 24 /* Address Base */
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#define ACR_MASK_POS 16 /* Address Mask */
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#define ACR_ENABLE 0x00008000 /* Enable address */
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#define ACR_USER 0x00000000 /* User mode access only */
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#define ACR_SUPER 0x00002000 /* Supervisor mode only */
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#define ACR_ANY 0x00004000 /* Match any access mode */
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#define ACR_CM_WT 0x00000000 /* Write through mode */
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#define ACR_CM_CP 0x00000020 /* Copyback mode */
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#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
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#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
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#define ACR_CM 0x00000060 /* Cache mode mask */
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#define ACR_WPROTECT 0x00000004 /* Write protect */
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#ifndef __ASSEMBLY__
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static inline void __m54xx_flush_cache_all(void)
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{
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/*
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* Use cpushl to push and invalidate all cache lines.
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* Gas doesn't seem to know how to generate the ColdFire
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* cpushl instruction... Oh well, bit stuff it for now.
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*/
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__asm__ __volatile__ (
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"nop\n\t"
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"clrl %%d0\n\t"
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"1:\n\t"
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"movel %%d0,%%a0\n\t"
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"2:\n\t"
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".word 0xf468\n\t"
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"addl #0x10,%%a0\n\t"
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"cmpl #0x00000800,%%a0\n\t"
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"blt 2b\n\t"
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"addql #1,%%d0\n\t"
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"cmpil #4,%%d0\n\t"
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"bne 1b\n\t"
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"movel #0xb6088500,%%d0\n\t"
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"movec %%d0,%%CACR\n\t"
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: : : "d0", "a0" );
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}
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#define __flush_cache_all() __m54xx_flush_cache_all()
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#endif /* __ASSEMBLY__ */
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#endif /* m54xxacr_h */
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