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Add Aspeed AST2400 and AST2600 binding for the Aspeed EDAC driver. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20201207090013.14145-1-troy_lee@aspeedtech.com
29 lines
811 B
Plaintext
29 lines
811 B
Plaintext
Aspeed BMC SoC EDAC node
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The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
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correction check).
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The memory controller supports SECDED (single bit error correction, double bit
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error detection) and single bit error auto scrubbing by reserving 8 bits for
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every 64 bit word (effectively reducing available memory to 8/9).
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Note, the bootloader must configure ECC mode in the memory controller.
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Required properties:
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- compatible: should be one of
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- "aspeed,ast2400-sdram-edac"
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- "aspeed,ast2500-sdram-edac"
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- "aspeed,ast2600-sdram-edac"
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- reg: sdram controller register set should be <0x1e6e0000 0x174>
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- interrupts: should be AVIC interrupt #0
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Example:
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edac: sdram@1e6e0000 {
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compatible = "aspeed,ast2500-sdram-edac";
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reg = <0x1e6e0000 0x174>;
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interrupts = <0>;
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};
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